Rocket Core

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Rocket Core is identified in the supplied evidence as an open-source RISC-V-based processor core. The ProcessorFuzz paper uses Rocket Core as an example when discussing hardware-fuzzing coverage behavior: its MulDiv multiplication unit contains a 130-bit remainder register that indirectly controls 98 mux-selection signals, and the paper reports that MulDiv dominated module-wise register coverage in a 24-hour Rocket Core fuzzing session.

First seen 5/24/2026

Last seen 6/6/2026

Evidence 13 chunks

Wiki v3

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Rocket Core

Rocket Core is an open-source, RISC-V-based processor core referenced in the ProcessorFuzz paper. The supplied evidence discusses it mainly as a case study for hardware-fuzzing coverage behavior rather than as a general architectural specification.

ProcessorFuzz context

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NEIGHBORHOOD

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RELATIONSHIPS

10 connections

Chisel HDL implements → 100% 4e

Rocket Core is designed in Chisel HDL.

RISC-V mentions → 100% 2e

The Rocket Core is described as an open-source RISC-V core.

MulDiv module ← part of 100% 2e

Rocket Core contains the MulDiv module.

Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms ← evaluates 90% 2e

The paper discusses Rocket Core as an open RISC-V implementation.

ProcessorFuzz ← evaluates 100% 2e

ProcessorFuzz was evaluated using the Rocket Core processor.

Coverage-Guided Pre-Silicon Fuzzing of Open-Source Processors based on Leakage Contracts ← evaluates 100% 2e

The paper performs an extensive evaluation on the in-order Rocket Core.

RISC-V ISA implements → 100% 1e

Rocket Core is a RISC-V processor core implementing the RISC-V ISA.

Rocket Chip SoC Generator depends on → 100% 1e

Rocket Core is generated using the Rocket Chip SoC Generator framework.

Branch Target Buffer ← part of 80% 1e

The Branch Target Buffer (BTB) is a component of the Rocket Core processor shown in coverage breakup.

Rocket Chip SoC Generator part of → 90% 1e

Rocket Core can be generated using the Rocket Chip SoC Generator framework.

LINKED ENTITIES

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ProcessorFuzz EVALUATES Extracted graph relationship

RISC-V ISA IMPLEMENTS Extracted graph relationship

Chisel HDL IMPLEMENTS Extracted graph relationship

Rocket Chip SoC Generator DEPENDS_ON Extracted graph relationship

MulDiv module PART_OF Extracted graph relationship

Branch Target Buffer PART_OF Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Rocket Core is described as an open-source RISC-V-based core. ProcessorFuzz: Processor Fuzzing with Control and

[2] ProcessorFuzz uses ISA simulation and CSR-transition information to identify interesting test inputs before RTL simulation. ProcessorFuzz: Processor Fuzzing with Control and

[3] Rocket Core's MulDiv multiplication unit contains a 130-bit remainder register that indirectly controls 98 mux-selection signals, and DIFUZZRTL ultimately tracks 98 bits of that register. ProcessorFuzz: Processor Fuzzing with Control and

[4] In a 24-hour Rocket Core fuzzing session, the MulDiv module dominated module-wise register coverage. ProcessorFuzz: Processor Fuzzing with Control and

[5] The supplied figure labels Rocket Core RTL with BTB, DCache, MulDiv, remainder-register, and other coverage components. ProcessorFuzz: Processor Fuzzing with Control and