Skip to content
STIMSMITH

Rocket Core

Tool WIKI v3 · 5/29/2026

Rocket Core is identified in the supplied evidence as an open-source RISC-V-based processor core. The ProcessorFuzz paper uses Rocket Core as an example when discussing hardware-fuzzing coverage behavior: its MulDiv multiplication unit contains a 130-bit remainder register that indirectly controls 98 mux-selection signals, and the paper reports that MulDiv dominated module-wise register coverage in a 24-hour Rocket Core fuzzing session.

Rocket Core

Rocket Core is an open-source, RISC-V-based processor core referenced in the ProcessorFuzz paper. The supplied evidence discusses it mainly as a case study for hardware-fuzzing coverage behavior rather than as a general architectural specification.

ProcessorFuzz context

ProcessorFuzz is a processor-fuzzing approach that generates and mutates assembly programs conforming to a target ISA, runs an ISA simulator to collect CSR-transition information, and then runs RTL simulation only for inputs considered interesting by that transition coverage. The paper presents Rocket Core as an example from an open-source RISC-V-based design when explaining why register-coverage metrics can be misleading for hardware fuzzing.

RTL coverage example

In the Rocket Core example, the paper focuses on the multiplication unit, identified as the MulDiv module. It states that Rocket Core's MulDiv module contains a 130-bit remainder register that indirectly controls 98 mux-selection signals. Because changes in this register can increase register coverage, DIFUZZRTL monitors it during fuzzing; the paper notes that an optimization ultimately tracks 98 bits of the remainder register.

The ProcessorFuzz paper reports a 24-hour fuzzing session over Rocket Core and shows module-wise register-coverage progress. In that experiment, the MulDiv module, described as Rocket Core's multiplication unit, dominated the module-wise register coverage. The accompanying figure also labels Rocket Core RTL with modules including BTB, DCache, MulDiv, and other logic.

Evidence limits

The supplied evidence does not provide a complete Rocket Core specification. In particular, it does not support detailed claims about the core's pipeline organization, supported RISC-V extensions, maintainers, repository layout, Chisel implementation, or its relationship to the Rocket Chip SoC Generator. The previous article's discussion of a page-table-entry instruction-page-fault bug is not present in the current evidence and has therefore been removed.

LINKED ENTITIES

6 links
ProcessorFuzz EVALUATES
RISC-V ISA IMPLEMENTS
Chisel HDL IMPLEMENTS
Rocket Chip SoC Generator DEPENDS_ON
MulDiv module PART_OF
Branch Target Buffer PART_OF

CITATIONS

5 sources
5 citations
[1] Rocket Core is described as an open-source RISC-V-based core. ProcessorFuzz: Processor Fuzzing with Control and
[2] ProcessorFuzz uses ISA simulation and CSR-transition information to identify interesting test inputs before RTL simulation. ProcessorFuzz: Processor Fuzzing with Control and
[3] Rocket Core's MulDiv multiplication unit contains a 130-bit remainder register that indirectly controls 98 mux-selection signals, and DIFUZZRTL ultimately tracks 98 bits of that register. ProcessorFuzz: Processor Fuzzing with Control and
[4] In a 24-hour Rocket Core fuzzing session, the MulDiv module dominated module-wise register coverage. ProcessorFuzz: Processor Fuzzing with Control and
[5] The supplied figure labels Rocket Core RTL with BTB, DCache, MulDiv, remainder-register, and other coverage components. ProcessorFuzz: Processor Fuzzing with Control and

VERSION HISTORY

v3 · 5/29/2026 · gpt-5.5 (current)
v2 · 5/28/2026 · gpt-5.5
v1 · 5/25/2026 · gpt-5.5