Branch Target Buffer

Concept

A Branch Target Buffer (BTB) is a dynamic branch-prediction component in the instruction-fetch path. The cited RISC-V superscalar processor description places the BTB in the IF unit’s dynamic predictor, where it records branch target PC addresses to speed prediction of taken-branch targets. The evidence also shows BTB-specific functional verification coverpoints and identifies BTB as a named block in Rocket Core RTL coverage/fuzzing context.

First seen 5/27/2026

Last seen 5/29/2026

Evidence 6 chunks

Wiki v3

WIKI

Overview

A Branch Target Buffer (BTB) is a branch-prediction structure used by the instruction-fetch path. In the cited RISC-V superscalar processor description, the Instruction Fetch (IF) unit fetches instructions from the instruction cache and predicts the next Program Counter (PC), and its dynamic predictor includes a Branch History Table (BHT), a Branch Target Buffer (BTB), and a Return Address Stack (RAS). [C1]

Within that dynamic predictor, the BTB records the target PC address of each branch instruction so the processor can determine branch-taken addresses more quickly. [C1]

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections

mispredicted path fuzzing ← uses 95% 2e

Mispredicted path fuzzing manipulates Branch Target Buffer entries to generate atypical addresses.

Logic Fuzzer ← uses 100% 2e

Logic Fuzzer fuzzes Branch Target Buffer entries to generate atypical instruction addresses.

Rocket Core part of → 80% 1e

The Branch Target Buffer (BTB) is a component of the Rocket Core processor shown in coverage breakup.

Instruction Fetch Unit part of → 98% 1e

The BTB is a component of the dynamic predictor in the instruction fetch unit.

branch predictor part of → 95% 1e

The BTB is a component of the branch predictor.

LINKED ENTITIES

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Rocket Core PART_OF Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] In the cited RISC-V superscalar processor description, the IF unit predicts the next PC and its dynamic predictor includes a BHT, BTB, and RAS; the BTB records branch target PC addresses to expedite branch-taken address determination. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The cited design’s decode-stage flush controller checks IF-stage branch predictions and flushes/redirects the pipeline on misprediction by comparing the resolved branch result with the stored initial prediction. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The IF-unit functional coverpoints include reading every line of the BTB array, writing every line of the BTB array, BTB full, and BTB empty conditions, alongside BHT and RAS coverpoints. [PDF] UVM-based verification of RISC-V superscalar processors

[4] ProcessorFuzz proposes a processor-fuzzing mechanism using CSR-transition coverage and ISA-simulator feedback, and its Rocket Core RTL coverage illustration labels BTB as a block in the coverage context. ProcessorFuzz: Processor Fuzzing with Control and