Instruction Fetch Unit
ConceptThe Instruction Fetch Unit (IFU) is a front-end processor subsystem responsible for fetching instructions from the instruction cache and predicting the next Program Counter. In RISC-V designs, it appears both in superscalar out-of-order cores (where it fetches two instructions per cycle and includes a BHT/BTB/RAS dynamic predictor) and in FPGA-targeted soft processors (where it must support the RISC-V compressed-instruction extension efficiently). It is also verified as a discrete UVM block, with constrained-random test sequences per interface and coverpoints targeting the branch-prediction structures.
First seen 5/28/2026
Last seen 7/6/2026
Evidence 8 chunks
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WIKI
Overview
The Instruction Fetch Unit (IFU) is the front-end subsystem of a processor responsible for fetching instructions from the instruction cache and predicting the next Program Counter (PC) address, i.e., the address of the next instruction to fetch. The IFU is part of the broader RISC-V processor front end and is studied both in the context of high-performance superscalar out-of-order cores and in FPGA-targeted soft-processor implementations.
Role in the pipeline
NEIGHBORHOOD
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5 connectionsThe instruction fetch unit is a component of the superscalar out-of-order processor.
The BHT is a component of the dynamic predictor in the instruction fetch unit.
The BTB is a component of the dynamic predictor in the instruction fetch unit.
The RAS is a component of the dynamic predictor in the instruction fetch unit.
The Instruction Fetch Unit is a key block of the RISC-V processor core.
LINKED ENTITIES
6 linksRISC-V PART_OF Extracted graph relationship
Branch History Table USES BHT is explicitly described in the evidence as a 256-entry table inside the IFU's dynamic predictor, with write/read/overflow/underflow coverpoints.
Branch Target Buffer USES BTB is explicitly described in the evidence as part of the IFU's dynamic predictor and as a coverpoint target with full/empty states.
Return Address Stack USES RAS is explicitly described in the evidence as part of the IFU's dynamic predictor with full/empty/overflow/underflow coverpoints.
Universal Verification Methodology VERIFIED_BY The IFU is verified using UVM in both the superscalar RISC-V work and the IJEDR block-level verification project.
Multi-Armed Bandit VERIFIED_BY The cited verification work explicitly applies an MAB-driven (UCB1) simulation flow to the IFU.
CITATIONS
16 sources16 citations — click to expand
[1] The IFU is the processor front-end subsystem that fetches instructions from the instruction cache and predicts the next PC, and it is part of the RISC-V processor front end. UVM-based verification of RISC-V superscalar processors
[2] In the cited two-way superscalar out-of-order RISC-V core, the IFU fetches two instructions per cycle and supplies them to a two-instruction decode stage. UVM-based verification of RISC-V superscalar processors
[3] The IFU's dynamic predictor includes a BHT (with GShare indexing), a BTB, and an RAS that together select likely next fetch addresses. UVM-based verification of RISC-V superscalar processors
[4] The IFU connects to the rest of the processor via four interfaces: Predictor Update, Decode, Pipeline Flush, and Instruction Cache, each driven by a distinct constrained-random test sequence. UVM-based verification of RISC-V superscalar processors
[5] Predictor Update interface parameters include backward/forward branch taken rates, invalid instruction rate, and function return rate, with backward branch sampled at 5%, 40%, or 80%. UVM-based verification of RISC-V superscalar processors
[6] Decode interface parameters include idle, invalid instruction, function call, and stall rates; idle/invalid/function-return probabilities must sum to 1 because they are mutually exclusive. UVM-based verification of RISC-V superscalar processors
[7] Pipeline Flush interface parameters are branch misprediction rate and branch instruction rate. UVM-based verification of RISC-V superscalar processors
[8] Instruction Cache interface parameters include backward branch rate, partial access rate, and miss rate. UVM-based verification of RISC-V superscalar processors
[9] Functional coverpoints for the IFU include write/read/overflow/underflow bins on a 256-line, 1024-counter BHT; full/empty BTB and RAS states; RAS overflow/underflow; and restart-event and half-access FSM transitions. UVM-based verification of RISC-V superscalar processors
[10] Coverage bins are considered fully covered when hit at least 100 times, and bins that reach the goal are removed from the active set. UVM-based verification of RISC-V superscalar processors
[11] The verification flow uses K = 40 virtual test sequences selected randomly so that each parameter level is used at least once. UVM-based verification of RISC-V superscalar processors
[12] An MAB-driven verification flow using the UCB1 algorithm is applied to the IFU, balancing exploration and exploitation when picking virtual sequences. UVM-based verification of RISC-V superscalar processors
[13] In the IJEDR block-level UVM verification project, the IFU is verified individually alongside other RISC-V core blocks (IDU, Execute Unit, LSU, Register File, CSR, Pipeline/Hazard, Exception Unit), using constrained-random stimulus, SVA, functional coverage, a Spike/custom reference model, and a scoreboard. Verification Of Risc-V Core Blocks Using Uvm
[14] The IJEDR project reports that all targeted units including the IFU were verified against the RISC-V specification, functional and assertion coverage goals were achieved, and critical corner-case bugs were identified and resolved. Verification Of Risc-V Core Blocks Using Uvm
[15] RVCoreP is a five-stage pipelined RISC-V RV32I soft processor whose IFU optimization, including a pipelined branch-prediction mechanism, is one of three methods used to raise operating frequency; it achieves 30.0% performance improvement over VexRiscv on FPGA. RVCoreP : An optimized RISC-V soft processor of five-stage pipelining
[16] RVCoreP-32IC is a RISC-V soft processor with an efficient IFU supporting compressed instructions, reducing program size by about 25% while improving performance by 42.5% (DMIPS), 41.1% (CoreMark), and 21.3% (Embench) over related work; implemented on a Xilinx Artix-7 FPGA. RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions