Instruction Fetch Unit

Concept

An Instruction Fetch Unit (IF unit) is the processor front-end subsystem that fetches instructions from the instruction cache and predicts the next program counter. In the cited two-way RISC-V superscalar out-of-order processor, the IF unit fetches two instructions per cycle and includes a dynamic branch-prediction structure built from a BHT, BTB, and RAS.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

The Instruction Fetch Unit (IF unit) is a front-end processor subsystem responsible for fetching instructions from the instruction cache and predicting the next Program Counter (PC) address, i.e., the address of the next instruction to fetch. In the cited two-way RISC-V superscalar out-of-order processor, the IF subsystem is part of the processor front end, comprises the instruction cache and a dynamic predictor module, and fetches two instructions per cycle for forwarding to the Instruction Decode stage.

Role in a superscalar out-of-order pipeline

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RELATIONSHIPS

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Superscalar Out-of-Order Processor part of → 98% 1e

The instruction fetch unit is a component of the superscalar out-of-order processor.

Branch History Table ← part of 98% 1e

The BHT is a component of the dynamic predictor in the instruction fetch unit.

Branch Target Buffer ← part of 98% 1e

The BTB is a component of the dynamic predictor in the instruction fetch unit.

Return Address Stack ← part of 98% 1e

The RAS is a component of the dynamic predictor in the instruction fetch unit.

LINKED ENTITIES

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Superscalar Out-of-Order Processor PART_OF Extracted graph relationship

Branch History Table PART_OF Extracted graph relationship

Branch Target Buffer PART_OF Extracted graph relationship

Return Address Stack PART_OF Extracted graph relationship

CITATIONS

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8 citations — click to expand

[1] In the cited two-way RISC-V superscalar out-of-order processor, the IF subsystem is part of the front end, comprises the instruction cache and a dynamic predictor module, and fetches two instructions per cycle for the Instruction Decode stage. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The IF unit is responsible for fetching instructions from the instruction cache and predicting the next PC address. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The IF unit's dynamic predictor includes a BHT, BTB, and RAS; the BHT predicts branch direction, the BTB records branch target PC addresses, and the RAS supplies predicted return PCs for function returns. [PDF] UVM-based verification of RISC-V superscalar processors

[4] During simulation, the IF unit is modeled with four separate interfaces, each driven by a distinct test sequence that mimics behavior when connected to the rest of the processor. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The Predictor Update interface receives resolved branch status from the execution stage, and the Decode interface provides validity and instruction-type information and triggers branch-prediction restart events. [PDF] UVM-based verification of RISC-V superscalar processors

[6] The Pipeline Flush interface issues a flush on branch misprediction, and the Instruction Cache interface fetches two instructions from the instruction cache for a current PC address. [PDF] UVM-based verification of RISC-V superscalar processors

[7] Representative IF-unit coverpoints include branch-prediction combinations, BHT reads and writes, BTB reads and writes and full/empty states, RAS full/empty/overflow/underflow states, and restart-event and half-access FSM transitions. [PDF] UVM-based verification of RISC-V superscalar processors

[8] The cited verification flow applies a multi-armed-bandit approach to IF-unit verification and uses UCB1 to balance exploration and exploitation when selecting test sequences. [PDF] UVM-based verification of RISC-V superscalar processors