Return Address Stack
ConceptA Return Address Stack (RAS) is a branch-prediction structure used to predict function-return targets. In the provided RISC-V superscalar processor evidence, it is part of the instruction-fetch unit’s dynamic predictor: decoded function calls provide return addresses, and return instructions pop an RAS entry to supply the next predicted program counter. The RAS is also relevant to processor-verification fuzzing because Logic Fuzzer techniques used to perturb branch-predictor targets can be applied to the RAS.
WIKI
Overview
A Return Address Stack (RAS) is a component of a processor’s dynamic branch predictor. In the cited RISC-V superscalar processor description, the instruction-fetch (IF) unit fetches instructions from the instruction cache and predicts the next Program Counter (PC), i.e. the address of the next instruction to fetch. The dynamic predictor in that IF unit includes a Branch History Table (BHT), a Branch Target Buffer (BTB), and a Return Address Stack.[1]
The RAS stores return addresses of decoded function calls. When a function-return instruction is encountered, the processor pops an entry from the RAS and uses that entry as the next predicted PC address.[2]
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