A branch predictor is a dynamic prediction mechanism in a processor instruction-fetch unit that predicts the next program-counter address to fetch. In the cited RISC-V superscalar processor evidence, the predictor includes a Branch History Table for taken/not-taken direction prediction, a Branch Target Buffer for branch target addresses, and a Return Address Stack for return addresses. Verification evidence also treats branch-predictor structures as a way to stress mispredicted paths: high prediction accuracy can leave speculative paths under-tested, while fuzzing can broaden BTB-predicted address ranges and increase instruction coverage on flushed paths.

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