branch predictor

Concept

A branch predictor is a dynamic prediction mechanism in a processor's Instruction Fetch (IF) unit that predicts the next Program Counter (PC). In cited RISC-V superscalar evidence (CVA5), the predictor comprises a Branch History Table (BHT) for taken/not-taken direction (using a GShare indexing scheme), a Branch Target Buffer (BTB) for branch target addresses, and a Return Address Stack (RAS) for return addresses. A flush controller in the Instruction Decode stage compares resolved branch outcomes to stored predictions and redirects the pipeline on misprediction. Cited sources describe prediction accuracy above 95% as a verification hazard for mispredicted paths. Cited RTL design evidence treats BHT/BTB sizes as configurable microarchitectural knobs. Cited TaPaFuzz work contributes microarchitecture fixes to the CVA5 RISC-V core allowing it to fully reset its caches and branch predictors between fuzzer runs. Public context highlights load-driven and graph-application branch-predictor research as ongoing optimization avenues.

First seen 5/27/2026

Last seen 7/12/2026

Evidence 11 chunks

Wiki v5

WIKI

Overview

A branch predictor is a dynamic prediction mechanism in a processor's Instruction Fetch (IF) unit. In cited RISC-V superscalar processor design, the IF unit fetches instructions from the instruction cache and predicts the next Program Counter (PC), i.e., the address of the next instruction to fetch. The dynamic predictor is described as an instrumental part of the IF unit. [citation: IF-unit-next-PC]

Main structures

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RELATIONSHIPS

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CVA5 RISC-V Core ← uses 100% 2e

CVA5 has a branch predictor that must be cleared between fuzzer runs.

mispredicted path fuzzing ← uses 90% 2e

Mispredicted path fuzzing forces branch predictor to produce taken predictions for testing.

Logic Fuzzer ← uses 100% 2e

Logic Fuzzer can fuzz branch predictor tables to exercise mispredicted paths.

table mutator ← uses 95% 2e

Table mutators fuzz branch predictor tables during simulation.

Return Address Stack ← part of 90% 1e

The RAS is a component of the branch predictor.

Parameterization part of → 90% 1e

Branch predictor structures are configurable microarchitectural knobs exposed through parameterization.

Branch History Table (BHT) ← part of 93% 1e

Branch History Table (BHT) is one of the configurable branch predictor structures.

Branch Target Buffer (BTB) ← part of 93% 1e

Branch Target Buffer (BTB) is one of the configurable branch predictor structures.

Superscalar Out-of-Order Processor part of → 95% 1e

The branch predictor is part of the instruction fetch unit of the processor.

Branch History Table ← part of 95% 1e

The BHT is a component of the branch predictor.

Branch Target Buffer ← part of 95% 1e

The BTB is a component of the branch predictor.

LINKED ENTITIES

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CVA5 RISC-V Core USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Cited TaPaFuzz work implements CF monitoring in hardware running in parallel to software execution to avoid the runtime overheads of software instrumentation-based monitoring. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[2] Cited TaPaFuzz contributes microarchitecture fixes to the CVA5 RISC-V core allowing it to fully reset its caches and branch predictors between fuzzer runs. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[3] Cited TaPaFuzz contributes an AXI wrapper for legalizing aborted AXI transfers occurring due to random partial design resets between fuzzer job runs; it operates solely on AXI and reset interfaces and is portable across RISC-V core microarchitectures and AXI components. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[4] Cited TaPaFuzz reports that the BRAM variant uses 54%-66% additional LUTs and registers versus a plain CVA5 RISC-V core PE at a 10 MHz lower frequency; the DRAM/DDR4 variant trades additional cache and branch-prediction logic for a 80 KiB reduction in BRAM footprint. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[5] LDBP targets branches dependent on hard-to-predict load data; augmenting a 150-Kbit IMLI with LDBP reduces average branch mispredictions by 20% and improves average IPC by 13.1% on SPEC CINT2006 and GAP benchmarks compared with a standalone 256-Kbit IMLI. Load Driven Branch Predictor (LDBP)

[6] Branch mispredictions are frequent in graph processing and branch predictors can be further optimized to handle misprediction-causing branches beyond memory-hierarchy improvements. Optimizing Branch Predictor for Graph Applications