Branch Target Buffer (BTB)

Concept

The Branch Target Buffer (BTB) is a hardware structure within a CPU's branch predictor that caches branch target addresses to accelerate instruction fetching. It is one of the primary structures supporting instruction fetch efficiency alongside the L1 instruction cache and the instruction TLB.

First seen 5/28/2026

Last seen 6/21/2026

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Branch Target Buffer (BTB)

Overview

The Branch Target Buffer (BTB) is a specialized hardware structure that is part of a CPU's branch prediction logic. It records the target Program Counter (PC) address of previously executed branch instructions so that the address can be determined quickly when the same branch is encountered again [chunk:ddb97f7c-4c0b-40b5-9a11-820c4d7125cd]. By caching target addresses, the BTB helps expedite the determination of branch-taken addresses during instruction fetch.

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Branch Target Buffer (BTB) is one of the configurable branch predictor structures.

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CITATIONS

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[1] The BTB records the target PC address of each branch instruction to expedite the determination of branch-taken addresses. UVM-based verification of RISC-V superscalar processors

[2] The BTB is one of the primary structures (alongside L1i and iTLB) critical to instruction fetch efficiency. Improving Instruction Fetch Efficiency via High-Level Program Map Traversal

[3] BTB size and associativity are configurable microarchitectural parameters in RISC-V cores. Inside RISC-V: Navigating the RTL Design & Verification Landscape

[4] BTB verification requires coverage of read/write to every BTB array line and full/empty states; example design has 256 lines with two read ports. UVM-based verification of RISC-V superscalar processors

[5] BTB design and implementation are relevant for compiler optimization and mitigation of hardware attacks such as Spectre. Branch Target Buffer Reverse Engineering on Arm