Branch History Table (BHT)

Concept

The Branch History Table (BHT) is a hardware structure within a processor's branch predictor that records the direction (taken or not-taken) of previously executed branches in order to predict the direction of future occurrences of the same branch. In the RISC-V superscalar processor described in the evidence, the BHT uses a GShare indexing scheme, contains 256 entries with 1024 counters, and works in tandem with the Branch Target Buffer (BTB) and the Return Address Stack (RAS) inside the Instruction Fetch (IF) unit's dynamic predictor. The BHT is also exposed as a configurable microarchitectural knob in parameterized RTL designs, where its size is one of the parameters that designers can tune alongside BTB size and other branch predictor structures.

First seen 5/28/2026

Last seen 6/21/2026

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Branch History Table (BHT)

Overview

The Branch History Table (BHT) is a memory structure used by a processor's branch predictor to record and exploit the historical outcomes of branch instructions. It is one of the key sub-components of a dynamic branch predictor, alongside the Branch Target Buffer (BTB) and the Return Address Stack (RAS) ^[1].

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Branch History Table (BHT) is one of the configurable branch predictor structures.

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CITATIONS

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[1] The BHT maintains a history of the outcomes of previous occurrences of each branch to predict the direction (taken/not-taken) of the current branch using a GShare indexing scheme. UVM-based verification of RISC-V superscalar processors

[2] The BHT, BTB, and RAS together form the dynamic predictor inside the Instruction Fetch unit. UVM-based verification of RISC-V superscalar processors

[3] The BHT has 256 entries and 1024 counters, with two read ports (one per fetched instruction). UVM-based verification of RISC-V superscalar processors

[4] BHT verification coverpoints include writes to every line, writes/reads to every counter, and overflow/underflow of every counter (1024 bins each), plus line-level and counter-level reads on both ports. UVM-based verification of RISC-V superscalar processors

[5] A coverage goal of at least 100 hits per bin is used to declare the BHT coverpoints fully covered. UVM-based verification of RISC-V superscalar processors

[6] In parameterized RISC-V RTL designs, BHT size is exposed as a microarchitectural knob alongside BTB size, pipeline depth, cache associativity, and bus interface selection. Inside RISC-V: Navigating the RTL Design & Verification Landscape

[7] The IF unit issues a BTB lookup for the target PC and a BHT lookup for the taken/not-taken direction for each of the two fetched instructions, then selects the next PC from PC+4, the BTB target, or the RAS. UVM-based verification of RISC-V superscalar processors

[8] On branch resolution at the execution stage, the predictor update interface signals the actual branch outcome to the IF unit, and the Flush Controller compares it with the BHT-sourced prediction stored in a FIFO, flushing the pipeline on a mismatch. UVM-based verification of RISC-V superscalar processors