Superscalar Out-of-Order Processor

Concept

A superscalar out-of-order processor is a high-performance CPU microarchitecture class discussed in the evidence in the context of speculative execution, branch prediction, IPC, and RISC-V verification. The provided implementation-oriented evidence centers on the superscalar Toooba core, whose verification instrumentation interacts with instruction picking, decode, superscalar fetch, commit/write-back reporting, and a Reorder Buffer.

First seen 5/28/2026

Last seen 6/8/2026

Evidence 12 chunks

Wiki v2

WIKI

Overview

A superscalar out-of-order processor is treated in the provided sources as a CPU microarchitecture class relevant to high-performance execution, speculation, branch prediction, and RISC-V verification. Public research context describes modern branch predictors as enabling superscalar, out-of-order processors to maximize speculative efficiency and performance, while also noting that remaining mispredictions can have a measurable impact on single-thread IPC. [C1]

Another public source discusses speculative execution as a standard feature in modern processors and evaluates an ISA redesign on both an in-order soft core and a superscalar out-of-order processor, placing this processor class in the context of Spectre-mitigation and non-speculative CPU research. [C2]

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

10 connections

Toooba ← implements 100% 3e

Toooba is a fork of RiscyOO and implements superscalar out-of-order execution.

Toooba ← implements 100% 2e

Toooba is a RISC-V 64-bit superscalar out-of-order processor.

Instruction Issue Unit ← part of 98% 1e

The instruction issue unit is part of the superscalar out-of-order processor.

reorder buffer ← part of 98% 1e

The ReOrder Buffer is a component of the superscalar out-of-order processor.

Load-Store Unit ← part of 95% 1e

The Load-Store Unit is part of the execution stage of the superscalar processor.

branch predictor ← part of 95% 1e

The branch predictor is part of the instruction fetch unit of the processor.

UCAM-CL-TR-984 ← uses 100% 1e

The thesis develops the first open CHERI implementation for a superscalar out-of-order processor.

RiscyOO ← implements 100% 1e

RiscyOO is a superscalar out-of-order application-class core.

Instruction Fetch Unit ← part of 98% 1e

The instruction fetch unit is a component of the superscalar out-of-order processor.

LINKED ENTITIES

1 links

Toooba IMPLEMENTS Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] Branch predictors are described as enabling superscalar, out-of-order processors to maximize speculative efficiency and performance, while mispredictions can affect IPC. Branch Prediction Is Not a Solved Problem: Measurements, Opportunities, and Future Directions

[2] BasicBlocker is evaluated on a superscalar out-of-order processor and is motivated by speculative-execution security concerns. BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster

[3] Toooba is described as a superscalar core whose DII integration involved instruction-cache access, vectors of picked instructions before decode, 16-bit instruction fragments, instruction picking, and decode reconstruction. Randomized Testing of RISC-V CPUs using Direct

[4] Toooba’s DII strategy added superscalar fetch and assigned IDs to compressed instruction fragments to support redirects, canceled instructions, and RVFI-DII synchronization. Randomized Testing of RISC-V CPUs using Direct

[5] For pipelined or superscalar microarchitectures, RVFI extraction may require preserving state for commit/write-back reporting; extending superscalar Toooba for RVFI-DII required two extra records per instruction in the Reorder Buffer, present only in simulation builds with RVFI. Randomized Testing of RISC-V CPUs using Direct

[6] RVFI exposes architecturally significant trace signals, while TestRIG extends RVFI with Direct Instruction Injection for instruction input and interactive verification with shrinking. Randomized Testing of RISC-V CPUs using Direct

[7] QCVEngine uses QuickCheck to generate instruction lists, send them over DII sockets, collect RVFI traces, compare results, and use generators/templates for instruction sequences and deeper states. Randomized Testing of RISC-V CPUs using Direct