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Register Renaming

Concept

Register renaming is a processor microarchitecture technique that maps architectural registers to a larger pool of physical registers to remove name dependencies such as WAR and WAW hazards. In the provided RISC-V superscalar out-of-order design, the register renaming stage uses a Free List, Register Alias Table, and Checkpoint Table to allocate physical destinations, translate sources, and recover speculative state after flushes.

First seen 5/28/2026
Last seen 5/28/2026
Evidence 4 chunks
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WIKI

Overview

Register renaming is a microarchitectural stage used in a superscalar out-of-order processor to eliminate register name dependencies, specifically Write-After-Read (WAR) and Write-After-Write (WAW) hazards. It does this by mapping architectural, or logical, registers from the instruction set architecture to a larger pool of physical registers. In the two-way RISC-V superscalar out-of-order processor described in the evidence, decoded instructions are sent to the Register Renaming stage after instruction decode, and up to two instructions can be renamed per cycle. [1]

How renaming works

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections
Feedback-Based Verification ← evaluates 95% 2e
The feedback-based verification technique is applied to the Register Renaming Sub-system.
Superscalar Out-of-Order Processor part of → 98% 1e
Register renaming is a component of the superscalar out-of-order processor.
Register Alias Table ← part of 98% 1e
The RAT is part of the register renaming stage hardware.
Free List ← part of 98% 1e
The Free List is part of the register renaming hardware.
Checkpoint Table ← part of 98% 1e
The Checkpoint Table is part of the register renaming stage.

LINKED ENTITIES

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Feedback-Based Verification EVALUATES Extracted graph relationship
Superscalar Out-of-Order Processor PART_OF Extracted graph relationship
Register Alias Table PART_OF Extracted graph relationship
Free List PART_OF Extracted graph relationship
Checkpoint Table PART_OF Extracted graph relationship

CITATIONS

4 sources
4 citations — click to collapse
[1] Register Renaming is a stage in the described two-way RISC-V superscalar out-of-order processor that eliminates WAR and WAW hazards by mapping architectural registers to a larger pool of physical registers, with up to two instructions renamed per cycle. UVM-based verification of RISC-V superscalar processors
[2] Register renaming with a merged register file uses physical register specifiers for destinations and sources, and the described stage includes a Free List, Register Alias Table, and Checkpoint Table. UVM-based verification of RISC-V superscalar processors
[3] The verification flow covered the processor's Instruction Fetch, Register Renaming, Issue, and ReOrder Buffer units. UVM-based verification of RISC-V superscalar processors
[4] A feedback-based verification technique was applied to the Register Renaming Sub-system and reported approximately 70% simulation-time savings compared with fixed-duration conventional simulation. UVM-based verification of RISC-V superscalar processors