Feedback-Based Verification

Technique

Feedback-Based Verification is an automated test-application technique that uses coverage feedback to adjust how long verification test sequences run. In the cited RISC-V superscalar processor verification work, it uses each sequence’s incremental contribution to functional coverage to assign more simulation cycles to productive sequences and replace or suppress unproductive ones, with reported simulation-time savings of about 70% when applied to a Register Renaming Sub-system.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

Feedback-Based Verification is a test-application technique for functional verification in which the verification environment observes the online quality of applied test sequences and uses that feedback to decide future simulation duration. In the cited UVM-based verification work on a 2-way superscalar out-of-order RISC-V processor, the technique is introduced as one of two automation methods whose shared goal is to increase functional coverage while decreasing test-application time. [C1]

The method is intended for situations where a verification team already has a set of direct or parameterized constrained-random sequences and a set of functional coverage goals, but the quality of those sequences is uncertain. The broader problem is how to apply the available sequences over multiple trials so that coverage quality is maximized. [C2]

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Functional Coverage uses → 95% 2e

The feedback-based mechanism uses functional coverage as the feedback signal to adjust test durations.

The feedback-based verification technique is applied to the Register Renaming Sub-system.

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CITATIONS

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[1] Feedback-Based Verification is presented as an automated test-application technique that aims to increase functional coverage and decrease test-application time by observing sequence quality online, assigning more cycles to higher-quality sequences, and replacing poor sequences. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The motivating test-application problem is how to apply a set of direct or parameterized constrained-random sequences with uncertain quality against functional coverage goals over multiple trials. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The feedback-based technique uses each sequence's incremental contribution to functional coverage to decide future execution duration, does not change sequence order, and can improve simulation time by optimizing duration alone. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The technique was validated on the UVM-based verification of the Register Renaming Sub-system using constrained-random sequences with different parameters and direct-test sequences. [PDF] UVM-based verification of RISC-V superscalar processors

[5] Compared with conventional simulation that gives each sequence the same predetermined number of cycles, the feedback-based method achieved higher functional coverage in substantially smaller simulation time, with about 70% simulation-time savings reported for different test-sequence sets. [PDF] UVM-based verification of RISC-V superscalar processors