Functional Coverage
ConceptIn the provided evidence, functional coverage is treated as a hardware design-verification target, benchmark, quantitative value-space metric, and feedback signal. The RISC-V DV framework is shown measuring it against RISC-V immediate-field value spaces (with branch and jump immediates exhibiting very low coverage), and the source paper identifies coverage-guided feedback loops that steer instruction-stream generation as a future-work direction. Public arXiv work treats it as both a closure target (with a 26.9% test-count reduction to reach 98.5% coverage on a commercial bus bridge) and a steering signal for LLM-driven assertion generation (9.57–15.69% gains in branch, statement, and toggle coverage).
First seen 5/24/2026
Last seen 6/9/2026
Evidence 61 chunks
Wiki v15
WIKI
Functional Coverage
In the provided sources, functional coverage is treated as an operational concept in hardware design verification rather than a formally defined term. Evidence positions it as a verification goal, a benchmark for comparing stimulus-generation methods, a quantitative metric measured against the value space of design inputs, and a feedback signal that steers further verification work.
RISC-V DV and immediate-field coverage
NEIGHBORHOOD
7 nodes · 9 edgesgraph · Functional Coverage · depth=1
RELATIONSHIPS
50 connections Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 10e
The paper uses functional coverage to guide test generation.
The paper integrates functional coverage as part of the fuzzing approach.
Coverage-guided Aging uses functional coverage to smooth distribution
The paper measures and reports functional coverage as a key verification metric.
Coverage-guided fuzzing uses coverage to guide test generation
The Profiler measures functional coverage metrics including event coverage.
Coverage-Observer measures functional coverage based on ISS execution state.
Coverage-Observer measures functional coverage based on ISS execution state
Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← evaluates 100% 2e
The paper evaluates its method based on its ability to increase functional coverage.
The paper evaluates its approach by measuring functional coverage improvements over random methods.
Genesys PE is evaluated based on functional coverage metrics.
Coverage-guided Aging implements functional coverage monitoring to guide instruction generation.
The UVM environment implements a functional coverage plan to measure verification completeness.
The paper evaluates functional coverage using SystemVerilog covergroup definitions.
ImperasFC is a functional coverage tool that auto-generates SystemVerilog coverage models for RISC-V ISA features.
Verdi is used for functional coverage reporting and analysis, viewing coverage results from ImperasFC.
Coverage closure is achieved by analyzing functional coverage gaps and targeting them with directed tests.
Coverage-Driven Verification uses functional coverage to measure how much of the design has been tested.
The feedback-based mechanism uses functional coverage as the feedback signal to adjust test durations.
Functional coverage is measured to validate that Genesys PE provides the same level of coverage as Genesys.
The endless randomized instruction stream generation uses functional coverage information to guide generation.
rvgen includes built-in functional coverage as an integrated feature.
Coverage-driven verification uses functional coverage metrics to guide verification.
Functional coverage is integrated as part of the coverage-guided fuzzing approach.
Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← uses 100% 2e
The paper's method biases test selection towards increasing functional coverage.
The paper introduces a novel functional coverage metric tailored for ISS verification.
The Coverage-Observer measures functional coverage based on the ISS execution state.
The UVM environment implements a functional coverage plan to measure verification completeness.
The functional coverage discussion mentions Assertion-Based Verification as a related verification technique.
eUVM features functional coverage constructs.
The Coverage-Observer measures functional coverage based on ISS execution state.
Simulation-based verification uses functional coverage as a proxy metric for design correctness.
The UVM testbench collects functional coverage metrics.
Functional coverage is a component of the UVM verification methodology
The technique biases selection towards tests that increase functional coverage.
The paper discusses functional coverage as a metric used in processor verification.
The paper implements a functional coverage model in the verification infrastructure.
A testbench includes functional coverage mechanisms.
UVM-based verification uses functional coverage as a quality metric.
UCB1 evaluates functional coverage to measure simulation effectiveness.
The RNN technique uses functional coverage data as its quality function for optimizing stimulus generation.
The MAB framework targets functional coverage goals as its optimization objective.
Coverage-directed test selection biases selection towards tests likely to increase functional coverage.
Functional coverage is a key metric and component of the design verification process.
Coverage-directed test selection biases test selection towards increasing functional coverage.
The paper demonstrates better performance on functional coverage than random or constrained-random approaches.
The paper evaluates functional coverage achieved by the code generation tools.
AI-driven test generation methods maximize functional coverage.
ISS-RTL co-simulation achieves high coverage across pipeline and control flows.
RISC-V DV computes functional coverage information using SystemVerilog covergroup definitions.
CITATIONS
7 sources7 citations — click to expand
[1] RISC-V DV is a CRV framework tailored for RISC-V with bug-hunting capabilities for the RISC-V base ISA, whose test strategies provide a good distribution of instructions tailored for the respective strategy. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[2] Immediate-field coverage measured by RISC-V DV: SHAMT 100% (32/32), I-Imm 87.77% (3595/4096), S-Imm 47.07% (1928/4096), B-Imm 5.18% (212/4096), J-Imm 0.01% (99 values), U-Imm 0.16% (1722 values), with the conclusion that branch and jump immediates can be further improved. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[3] Most RISC-V general-purpose registers were accessed 10,000–30,000 times, with x0 accessed ~90,000 times because x0 is hardwired to zero and has only a single unique value; the relation between number of accesses and number of unique values is mostly consistent across registers. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[4] JALR is a major outlier in instruction coverage because it is a register-based jump that is difficult to test in a randomized way since arbitrary jumps can cause runtime errors; the main instruction distribution sits at around 200 instructions across classes. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[5] Future work to boost CRV for RISC-V includes integrating coverage information in a feedback loop to guide instruction stream generation towards maximizing coverage goals faster, which requires dynamically evolving SystemVerilog/UVM constraint descriptions at runtime. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[6] Novel test selectors accelerate functional coverage closure in simulation-based verification with performance not impacted by coverage holes, straightforward implementation, and relatively low computational expense; one selector achieves a 26.9% reduction in simulated tests to reach 98.5% coverage on a commercial bus bridge, outperforming two prior selectors by factors of 13 and 2.68. Detecting Stimuli with Novel Temporal Patterns to Accelerate Functional Coverage Closure
[7] CoverAssert uses functional coverage feedback to drive iterative LLM SystemVerilog assertion generation by clustering semantic and AST-based structural features, mapping them to specifications, and prioritizing uncovered points; on four open-source designs it improves average branch coverage by 9.57%, statement coverage by 9.64%, and toggle coverage by 15.69% when integrated with AssertLLM and Spec2Assertion. CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations