Free List
ConceptIn register renaming hardware, a Free List (FL) is a FIFO structure that holds available physical destination registers. During renaming, it supplies a free physical register for an instruction's logical destination register, and after certain pipeline flushes, registers allocated after the offending branch are returned to it.
First seen 5/28/2026
Last seen 5/28/2026
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Definition
A Free List (FL) is a hardware FIFO used in a register-renaming stage to manage available physical destination registers, or Pdsts. The Pdst entries are initialized in the Free List when a processor core is powered on.
Role in register renaming
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1 connectionsThe Free List is part of the register renaming hardware.
LINKED ENTITIES
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[1] A Free List is a FIFO in the register-renaming stage where physical destination registers are initialized when a core powers on. [PDF] UVM-based verification of RISC-V superscalar processors
[2] During register renaming, a free Pdst is allocated from the Free List to rename an instruction's logical destination register. [PDF] UVM-based verification of RISC-V superscalar processors
[3] The allocated Pdst is sent to the Reservation Station, and when the instruction executes it updates the physical register identified by that Pdst. [PDF] UVM-based verification of RISC-V superscalar processors
[4] The Free List is part of the register-renaming stage along with the Register Alias Table and Checkpoint Table. [PDF] UVM-based verification of RISC-V superscalar processors
[5] After a mispredicted branch flush, restoration returns to the Free List the Pdsts allocated after the offending instruction. [PDF] UVM-based verification of RISC-V superscalar processors