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Free List

Concept WIKI v1 · 5/28/2026

In register renaming hardware, a Free List (FL) is a FIFO structure that holds available physical destination registers. During renaming, it supplies a free physical register for an instruction's logical destination register, and after certain pipeline flushes, registers allocated after the offending branch are returned to it.

Definition

A Free List (FL) is a hardware FIFO used in a register-renaming stage to manage available physical destination registers, or Pdsts. The Pdst entries are initialized in the Free List when a processor core is powered on.

Role in register renaming

In a register-renaming design with a merged physical register file, logical register specifiers are replaced with physical register specifiers. For an instruction that produces a result, the Free List provides a free Pdst to rename the instruction's logical destination register. That Pdst is then sent to the Reservation Station, where the renamed instruction waits for execution. When the instruction executes, it updates the physical register identified by its Pdst.

The Free List is one of the hardware arrays in the register-renaming stage, alongside the Register Alias Table (RAT) and the Checkpoint Table (CKPT). The RAT tracks the most recent logical-to-physical register mappings, while the CKPT stores snapshots of the RAT for branch recovery.

Recovery behavior

On a pipeline flush caused by a mispredicted branch, the register-renaming state can be restored using a checkpoint. In that restoration process, the RAT is restored from the checkpoint associated with the offending branch, and the Pdsts allocated after that offending instruction are returned to the Free List.

LINKED ENTITIES

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Register Renaming PART_OF

CITATIONS

5 sources
5 citations
[1] A Free List is a FIFO in the register-renaming stage where physical destination registers are initialized when a core powers on. [PDF] UVM-based verification of RISC-V superscalar processors
[2] During register renaming, a free Pdst is allocated from the Free List to rename an instruction's logical destination register. [PDF] UVM-based verification of RISC-V superscalar processors
[3] The allocated Pdst is sent to the Reservation Station, and when the instruction executes it updates the physical register identified by that Pdst. [PDF] UVM-based verification of RISC-V superscalar processors
[4] The Free List is part of the register-renaming stage along with the Register Alias Table and Checkpoint Table. [PDF] UVM-based verification of RISC-V superscalar processors
[5] After a mispredicted branch flush, restoration returns to the Free List the Pdsts allocated after the offending instruction. [PDF] UVM-based verification of RISC-V superscalar processors