Load-Store Unit

Concept

A Load-Store Unit is the execution-stage functional unit responsible for load and store memory operations in the cited RISC-V superscalar processor. In that design, it is a two-cycle pipelined module containing the data cache and surrounding logic; it computes addresses, handles load forwarding checks, accesses or stalls on the data cache, and delays store updates until the store is non-speculative at the head of the reorder buffer.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

In the cited RISC-V superscalar processor, the Load-Store Unit is one of the functional units in the execution stage, alongside the integer ALU and the branch resolve unit. The execution stage also includes data-routing logic needed to connect instructions to these functional units.

The Load-Store Unit is described as a two-cycle pipelined module that contains the data cache and its surrounding logic. It handles memory-access instructions, with distinct behavior for stores and loads.

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Superscalar Out-of-Order Processor part of → 95% 1e

The Load-Store Unit is part of the execution stage of the superscalar processor.

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CITATIONS

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[1] The execution stage of the cited RISC-V superscalar processor includes the integer ALU, branch resolve unit, and Load-Store Unit. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The Load-Store Unit is a two-cycle pipelined module containing the data cache and surrounding logic. [PDF] UVM-based verification of RISC-V superscalar processors

[3] For stores, the first Load-Store Unit stage calculates the address, and stores may modify memory only after becoming non-speculative at the ROB head. [PDF] UVM-based verification of RISC-V superscalar processors

[4] For loads, the first stage calculates the address and checks for possible forwarding from the ROB; absent a hit, the load proceeds to the second stage. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The second Load-Store Unit stage mainly consists of the data cache and related logic, where an instruction may be served directly, pushed into the data cache, or stalled. [PDF] UVM-based verification of RISC-V superscalar processors

[6] The ROB enables in-order commit despite out-of-order completion and tracks speculative instructions, which is used to prevent stores from modifying cache contents before they are non-speculative. [PDF] UVM-based verification of RISC-V superscalar processors

[7] The random instruction generator can be configured to create direct tests targeting the Load/Store Unit by setting load and store probabilities, producing load/store instruction sequences. [PDF] UVM-based verification of RISC-V superscalar processors

[8] The generator includes a memory-access address dependency parameter for generating load/store instruction pairs targeting the same memory address. [PDF] UVM-based verification of RISC-V superscalar processors