Overview

In the cited RISC-V superscalar processor, the Load-Store Unit is one of the functional units in the execution stage, alongside the integer ALU and the branch resolve unit. The execution stage also includes data-routing logic needed to connect instructions to these functional units.

The Load-Store Unit is described as a two-cycle pipelined module that contains the data cache and its surrounding logic. It handles memory-access instructions, with distinct behavior for stores and loads.

Pipeline behavior

Store operations

For store instructions, the first Load-Store Unit stage calculates the target address. Stores are not allowed to modify memory immediately: they may update memory only after they have been deemed non-speculative. In the cited processor, this happens when the store reaches the head of the reorder buffer (ROB).

Load operations

For load instructions, the first stage calculates the address and checks whether the load can be forwarded from the ROB. If no forwarding hit occurs, the load is routed to the second pipeline stage.

The second stage mainly consists of the data cache and associated logic. In this stage, information is retrieved from the pipeline register, and the instruction is either served directly, pushed into the data cache, or stalled while waiting.

Relationship with the reorder buffer

The reorder buffer supports out-of-order completion while enforcing in-order commit. It also tracks speculative instructions. This tracking is specifically used for store instructions, because stores must not modify cache contents until they are non-speculative.

Verification targeting

The cited verification work describes a random instruction generator that can be configured to generate direct tests targeting the Load/Store Unit. Setting load and store instruction probabilities to 50 produces load/store-heavy instruction sequences, such as combinations of address setup instructions with LW, SH, SW, LHU, and LBU operations.

The same generator includes a memory-access address dependency parameter, defined as the probability of generating a load/store instruction pair targeting the same memory address. This makes load/store address interactions an explicit part of verification stimulus generation.