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Toooba

CodeArtifact

Toooba is referenced in TestRIG evidence as a superscalar RISC-V CPU core that was instrumented for RVFI-DII-based interactive verification. Its integration required changes around instruction injection, superscalar fetch, compressed-instruction fragment handling, and additional simulation-only Reorder Buffer records for RVFI reporting.

First seen 5/27/2026
Last seen 7/3/2026
Evidence 7 chunks
Wiki v1

WIKI

Overview

Toooba is a superscalar CPU core discussed in the context of randomized testing of RISC-V CPUs with TestRIG and RVFI-DII. The evidence describes Toooba as a superscalar core and contrasts its RVFI-DII instrumentation with simpler single-issue designs such as Piccolo and Flute. [Toooba core classification]

RVFI-DII integration

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NEIGHBORHOOD

5 nodes · 10 edges
graph · Toooba · depth=1

RELATIONSHIPS

8 connections
TestRIG ← evaluates 95% 11e
TestRIG has been used to test Toooba, a superscalar out-of-order RISC-V processor.
RISC-V implements → 100% 6e
Toooba is a RISC-V out-of-order superscalar CPU implementation.
RVFI-DII implements → 90% 6e
Toooba is instrumented with RVFI-DII for use in TestRIG.
RVFI-DII uses → 100% 4e
Toooba is instrumented with RVFI-DII using superscalar fetch and ID assignment.
RTL implements → 90% 3e
Toooba is an RTL design that required custom pipeline instrumentation for RVFI-DII.
HARTBREAKER ← evaluates 100% 3e
HARTBREAKER was evaluated on the Toooba RISC-V CPU.
Superscalar Out-of-Order Processor implements → 100% 2e
Toooba is a RISC-V 64-bit superscalar out-of-order processor.
out-of-order execution implements → 100% 1e
Toooba is an out-of-order superscalar CPU.

LINKED ENTITIES

3 links
TestRIG EVALUATES Extracted graph relationship
RISC-V IMPLEMENTS Extracted graph relationship
RVFI-DII USES Extracted graph relationship

CITATIONS

6 sources
6 citations — click to expand
[1] Toooba core classification Randomized Testing of RISC-V CPUs using Direct
[2] RVFI-DII role Randomized Testing of RISC-V CPUs using Direct
[3] Toooba DII instrumentation path Randomized Testing of RISC-V CPUs using Direct
[4] Toooba sequence-ID adaptation Randomized Testing of RISC-V CPUs using Direct
[5] Toooba RVFI reporting overhead Randomized Testing of RISC-V CPUs using Direct
[6] TestRIG verification workflow Randomized Testing of RISC-V CPUs using Direct