Overview

Toooba is a superscalar CPU core discussed in the context of randomized testing of RISC-V CPUs with TestRIG and RVFI-DII. The evidence describes Toooba as a superscalar core and contrasts its RVFI-DII instrumentation with simpler single-issue designs such as Piccolo and Flute. [Toooba core classification]

RVFI-DII integration

TestRIG extends the RISC-V Formal Interface (RVFI) with Direct Instruction Injection (DII): DII supplies instruction input, while RVFI supplies trace output, enabling interactive verification and automated simplification and shrinking of failing cases. [RVFI-DII role]

For Toooba, the RVFI-DII integration initially retained the unmodified instruction-cache access path and substituted the vector of picked instructions before decode. Later, to debug instruction picking itself, the integration bypassed the instruction cache and provided 16-bit instruction fragments directly to the pipeline, relying on Toooba's instruction picker and decode logic to reconstitute the intended DII instruction sequence. [Toooba DII instrumentation path]

Handling dropped instructions and superscalar fetch

RVFI-DII requires one RVFI trace entry for each injected DII instruction, so synchronization is needed when instructions are canceled or dropped in a pipeline. The mature approach described in the evidence attaches a sequence ID to each RVFI instruction and carries it through the pipeline. This approach was adapted to Toooba by adding superscalar fetch and assigning IDs to compressed instruction fragments. [Toooba sequence-ID adaptation]

RVFI reporting overhead in simulation

Because complex RTL designs such as pipelined or superscalar microarchitectures may need to preserve additional state until commit or write-back, extending Toooba for RVFI-DII required two extra records per instruction in the Reorder Buffer. The evidence states that these records are present only when built for simulation with RVFI, so they are not physical design overhead. [Toooba RVFI reporting overhead]

Relationship to TestRIG

Toooba appears as an RVFI-DII-enabled target in the TestRIG verification context. TestRIG's QuickCheck-based QCVEngine sends generated instruction sequences over DII sockets, collects RVFI traces, compares those traces, and can shrink failing instruction sequences. [TestRIG verification workflow]