RTL

Concept

RTL (register transfer level) is the implementation-level hardware representation used in RISC-V design, verification, and LLM-assisted code generation. Across the evidence it is (1) the code artifact that EDA automation systems (RTL++, ACE-RTL) try to generate, (2) the HDL implementation form that participates in tandem verification (TestRIG, Difftest, ISS-driven verification, UVM-TLM, symbolic co-simulation, PFV, riscv-formal, FERIVer) against formal models and ISA simulators, (3) the model-under-test in processor verification flows such as co-simulation, random instruction generation (RISCV-DV), differential fuzzing (DifuzzRTL), AI-driven stimulus generation, and statistical fault injection (Chiffre), and (4) the target of mutation-based testing that exercises microarchitectural coverage beyond model coverage (e.g., the TestRIG framework's RTL-mutation extension). Concrete open RTL cores in the evidence include Rocket, BOOM, RI5CY (PULP), and Toooba, typically expressed in Chisel.

First seen 5/25/2026

Last seen 6/9/2026

Evidence 48 chunks

Wiki v11

WIKI

Overview

RTL stands for register transfer level, a hardware design/code representation that in the provided evidence serves four principal roles:

the code artifact that recent EDA automation systems try to generate more accurately,
the HDL implementation that is exercised in tandem verification alongside a formal model and an ISA simulator,
the model-under-test in processor verification flows such as co-simulation, random instruction generation, coverage-guided fuzzing, and statistical fault injection, and
the target of mutation-based testing that perturbs the RTL itself to exercise microarchitectural behaviour beyond architectural model coverage.

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NEIGHBORHOOD

1 nodes · 0 edges

graph · RTL · depth=1

RELATIONSHIPS

19 connections

RTL Fuzzing ← uses 100% 6e

RTL fuzzing operates on RTL (register transition level) designs to verify CPU circuits.

Toooba ← implements 90% 3e

Toooba is an RTL design that required custom pipeline instrumentation for RVFI-DII.

INSTILLER ← uses 100% 3e

Instiller targets RTL designs for CPU verification.

Functional Verification of a RISC-V Vector Accelerator ← evaluates 90% 2e

The paper evaluates the RTL design of the vector accelerator through functional verification.

Cross-Level Verification ← uses 90% 2e

Cross-level verification uses an RTL core in co-simulation with a reference ISS.

ImperasDV ← evaluates 96% 2e

ImperasDV compares RTL execution against a golden reference model to detect mismatches.

Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation ← uses 100% 2e

The paper operates on RTL designs for verification purposes.

UVM ← evaluates 90% 2e

The UVM testbench is used for verifying the RTL design of the vector accelerator.

ISS-RTL Co-Simulation ← uses 95% 2e

ISS-RTL co-simulation interfaces an ISS with RTL testbenches.

Design Under Test ← uses 90% 1e

RTL designs serve as the Design Under Test in verification setups.

Mutation-Based Testing ← evaluates 80% 1e

The mutation framework could be adapted to allow mutations to the RTL of a particular implementation.

Processor Verification ← uses 100% 1e

Processor verification is performed at the RTL level.

VCS ← evaluates 97% 1e

VCS is a high-performance RTL simulation platform that executes tests against RTL.

riscv-dv ← depends on 1e

RISCV-DV depends on an RTL simulator to run.

reference model comparison compares with → 90% 1e

When the reference model and RTL differ, engineers analyze whether the RTL behavior is acceptable.

Cross-Level Processor Verification ← uses 100% 1e

Cross-level processor verification targets verification at the RTL level.

TestRIG ← depends on 80% 1e

TestRIG requires RTL designs to implement custom pipeline instrumentation for DII support.

DiffTest ← uses 95% 1e

Difftest operates on an RTL processor, monitoring instruction commits and state updates.

emu ← implements 93% 1e

emu is the compiled RTL simulation executable for XiangShan used in difftest flows.

LINKED ENTITIES

2 links

Mutation-Based Testing EVALUATES Extracted graph relationship

riscv-dv GENERATES_TESTS_FOR RISC-V DV is a Google-developed CRV framework for RISC-V that produces randomized assembly instruction streams for RTL core simulation in a cross-level setting with a reference ISS, supporting RV32IMAFDC/RV64IMAFDC, page tables, privileged CSRs, and traps/interrupts.

CITATIONS

9 sources

9 citations — click to expand

[1] TestRIG extensions add validation of generated tests, support for minimal static unit tests, and tooling for catching lockup bugs, tracking runs in an SQLite database and using QuickCheckVEngine's shrinking mechanism to produce single-digit-instruction counterexamples. Who tests the TestRIG? Tooling for randomised tandem verification

[2] The TestRIG framework can be adapted to allow mutations to the RTL of a particular implementation, testing for microarchitectural coverage rather than just model coverage, building a library of short minimal traces via one-line-at-a-time mutations. Who tests the TestRIG? Tooling for randomised tandem verification

[3] The TestRIG extensions reproduced decode issues in Toooba, surfaced a rare branch-prediction lockup in Toooba's fetch stage, and identified a fatal assert in a version of the Sail model. Who tests the TestRIG? Tooling for randomised tandem verification

[4] riscv-formal defines standard instruction checks, PC checks (pc_fwd, pc_bwd), register checks, and causality checks (causal, causal_mem, causal_io) implemented via genchecks.py over a standard RVFI wrapper interface and driven by a bounded model check. Verification procedure - RISC-V Formal documentation

[5] riscv-formal sby scripts use [script-defines], [verilog-files]/[vhdl-files], [script-sources], and [defines] sections to wire core source files and check-specific code into a bounded model check, with a [depth] section specifying reset cycles and execution depth. Verification procedure - RISC-V Formal documentation

[6] The CRV study for RISC-V is built around the RISC-V DV framework from Google and targets cross-level test generation combining a reference ISS with an RTL core simulation; future work includes extracting constraints from CoreDSL, integrating dynamic ISS state into UVM constraint generation, FPGA/parallel acceleration, and AI methods to detect susceptible regions in RTL cores. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[7] The CRV study surveys RISC-V DV, RISC-V compliance, RISC-V tests, the RISC-V torture test generator, the RISC-V virtual prototype, OneSpin 360 DV RISC-V Verification App, and the RISC-V formal verification framework as open infrastructure for RISC-V verification. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[8] RTL++ uses textualized control-flow and data-flow graphs of RTL code to improve LLM-based code generation, outperforming state-of-the-art models fine-tuned for RTL on the VerilogEval benchmark's Pass@1/5/10 metric and on the RTLLM1.1 model. RTL++: Graph-enhanced LLM for RTL Code Generation

[9] ACE-RTL unifies an RTL-specialized LLM (trained on 1.7M RTL samples) with a frontier reasoning LLM through generator/reflector/coordinator components that iteratively refine RTL toward functional correctness, achieving up to a 41.02% pass-rate improvement over 14 baselines on the CVDP benchmark. ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs