golden model ISS

Concept

In the Ibex core verification flow, a golden model ISS is a reference Instruction Set Simulator whose execution trace is compared against the RTL core's trace to determine simulation correctness. It is used as the trusted reference inside the end-to-end RTL/ISS co-simulation flow, primarily for register writeback comparison, and is supplemented by the RISCV-DV handshaking mechanism for scenarios involving external stimulus.

First seen 6/6/2026

Last seen 6/6/2026

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Overview

In the Ibex core verification environment, a golden model ISS (Instruction Set Simulator) is a trusted software reference model whose behavior is compared against the RTL implementation of the core to determine whether a given simulation produces a correct result. It is the last-stage reference in the end-to-end RTL/ISS co-simulation flow, where the trace log produced by the core and the trace log produced by the chosen golden model ISS are both parsed and compared.

Role in the co-simulation flow

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RELATIONSHIPS

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RTL/ISS co-simulation ← uses 1e

RTL/ISS co-simulation uses a golden model ISS to compare register writeback data.

LINKED ENTITIES

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RTL/ISS co-simulation USES The evidence explicitly describes the golden model ISS as the reference whose trace log is parsed and compared inside the end-to-end RTL/ISS co-simulation flow, which matches an incoming USES relation from RTL/ISS co-simulation to the golden model ISS.

CITATIONS

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[1] A golden model ISS is used as the reference model in the end-to-end RTL/ISS co-simulation flow, where both the core's trace log and the ISS's trace log are parsed to collect register writeback information and compared for correctness. Verification — Ibex Documentation

[2] The trace log comparison verifies that the core writes the correct data to the correct registers in the correct order. Verification — Ibex Documentation

[3] ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus such as interrupts and debug requests. Verification — Ibex Documentation

[4] The RISCV-DV handshaking mechanism is used to let the core send status information to the testbench during program execution, enabling verification of interrupt handler entry, Debug Mode entry, and CSR updates. Verification — Ibex Documentation

[5] The signature address used by the Ibex testbench for the RISCV-DV handshaking is 0x8ffffffc. Verification — Ibex Documentation

[6] The handshaking mechanism is extensively used to provide runtime verification for external debug requests, interrupt assertions, and memory faults. Verification — Ibex Documentation

[7] Because the ISS trace log will not contain any execution information in the debug ROM or in any interrupt handler code, only the final values contained in every register at the end of the test are compared between the core and the golden model ISS. Verification — Ibex Documentation