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STIMSMITH

RTL/ISS co-simulation

Concept
First seen 6/6/2026
Last seen 6/6/2026
Evidence 1 chunks

NEIGHBORHOOD

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RELATIONSHIPS

8 connections
trace log uses → 1e
RTL/ISS co-simulation uses trace logs from both the core and the golden model ISS to verify correctness.
golden model ISS uses → 1e
RTL/ISS co-simulation uses a golden model ISS to compare register writeback data.
register writeback comparison uses → 1e
RTL/ISS co-simulation uses register writeback comparison to verify processor correctness.
handshaking mechanism uses → 1e
RTL/ISS co-simulation uses the handshaking mechanism from RISCV-DV to support external stimulus scenarios.
Ibex ← uses 1e
The Ibex core verification uses the RTL/ISS co-simulation flow.
RTL simulation uses → 1e
RTL/ISS co-simulation employs RTL simulation as one of its core techniques.
instruction-set simulation uses → 1e
RTL/ISS co-simulation employs instruction-set simulation as one of its core techniques.
Makefile ← part of 1e
The Makefile controls the entirety of the RTL/ISS co-simulation flow.