Ibex

Tool

Ibex is a small 32-bit RISC-V CPU core, formerly known as zero-riscy. Its public repository is primarily SystemVerilog, and it is listed among TestRIG-compatible RISC-V implementations used in randomized CPU testing research.

First seen 5/30/2026

Last seen 7/16/2026

Evidence 21 chunks

Wiki v1

WIKI

Overview

Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy. Its public lowRISC/ibex repository identifies the implementation language as SystemVerilog. As of the provided GitHub metadata, the repository had 1,892 stars, 741 forks, and was updated on 2026-05-28.

Role in RISC-V testing

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NEIGHBORHOOD

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RELATIONSHIPS

23 connections

RISC-V implements → 100% 5e

Ibex implements the RISC-V ISA.

TestRIG ← evaluates 95% 3e

TestRIG evaluates Ibex as a RISC-V implementation.

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors ← mentions 95% 2e

The paper mentions Ibex as a RISC-V core supported by Chipyard and used in security research.

Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection ← evaluates 100% 2e

The paper surveys bugs in Ibex and uses it as a target for ENCARSIA evaluation.

riscv-dv uses → 1e

The Ibex testbench uses RISCV-DV's handshaking mechanism for external stimulus verification.

UVM testbench uses → 1e

The Ibex core verification uses a UVM testbench framework as indicated by the UVM directory structure.

lowRISC published by → 1e

Ibex is published and maintained by lowRISC on GitHub.

Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches ← evaluates 90% 1e

Case study uses the Ibex processor to demonstrate the method.

RISC-V targets ISA → 98% 1e

Direct mention of the RISC-V Ibex core.

RV32I targets ISA → 86% 1e

Paper states RV32I configuration option for Ibex register file.

RV32E targets ISA → 86% 1e

Paper states RV32E configuration option for Ibex register file.

HDL implements → 100% 1e

Ibex is implemented in SystemVerilog HDL.

Chipyard ← uses 90% 1e

Chipyard supports configuration of SoCs based on Ibex.

formal verification uses → 1e

Ibex uses formal verification to ensure architectural correctness and security.

Trace Equivalence implements → 1e

Ibex implements trace equivalence verification against the Sail RISC-V model.

Formal Property Verification implements → 1e

Ibex implements Formal Property Verification for its instruction cache.

top.sv ← uses 1e

top.sv instantiates the Ibex core (ibex_top) for trace equivalence verification.

Control and Status Register evaluates → 1e

Ibex formally evaluates the Control and Status Register model.

Instruction Cache ← part of 1e

Ibex has an instruction cache (ibex_icache) as a component.

lowRISC authored by → 1e

Ibex is authored and maintained by lowRISC, as evidenced by the GitHub repository URL.

SystemVerilog uses → 85% 1e

Ibex is written in SystemVerilog.

Verilator depends on → 1e

Ibex depends on Verilator for its build process within TestRIG.

RTL/ISS co-simulation uses → 1e

The Ibex core verification uses the RTL/ISS co-simulation flow.

LINKED ENTITIES

3 links

TestRIG EVALUATES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

SystemVerilog USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy. lowRISC/ibex

[2] The public Ibex repository metadata identifies SystemVerilog as the repository language and reports 1,892 stars, 741 forks, and an update time of 2026-05-28T16:04:10Z. lowRISC/ibex

[3] The TestRIG paper lists Ibex among implementations in the TestRIG ecosystem and describes Ibex and Piccolo as simple 32-bit implementations. Randomized Testing of RISC-V CPUs using Direct

[4] TestRIG-compatible implementations use RVFI-DII instrumentation and are expected to provide a common architectural environment including reset behavior and an 8 MiB memory region at address 0x80000000. Randomized Testing of RISC-V CPUs using Direct

[5] The TestRIG repository collates TestRIG-compatible implementations and verification engines and is intended to support standardized RISC-V testing based on instrumentation of open implementations. Randomized Testing of RISC-V CPUs using Direct