Ibex

Tool

Ibex is a small 32-bit RISC-V CPU core, formerly known as zero-riscy. Its public repository is primarily SystemVerilog, and it is listed among TestRIG-compatible RISC-V implementations used in randomized CPU testing research.

First seen 5/30/2026

Last seen 6/6/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy. Its public lowRISC/ibex repository identifies the implementation language as SystemVerilog. As of the provided GitHub metadata, the repository had 1,892 stars, 741 forks, and was updated on 2026-05-28.

Role in RISC-V testing

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections

TestRIG ← evaluates 95% 2e

TestRIG evaluates Ibex as a RISC-V processor implementation.

RISC-V implements → 90% 1e

Ibex is a simple 32-bit RISC-V implementation.

SystemVerilog uses → 85% 1e

Ibex is written in SystemVerilog.

RTL/ISS co-simulation uses → 1e

The Ibex core verification uses the RTL/ISS co-simulation flow.

riscv-dv uses → 1e

The Ibex testbench uses RISCV-DV's handshaking mechanism for external stimulus verification.

UVM testbench uses → 1e

The Ibex core verification uses a UVM testbench framework as indicated by the UVM directory structure.

lowRISC published by → 1e

Ibex is published and maintained by lowRISC on GitHub.

LINKED ENTITIES

3 links

TestRIG EVALUATES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

SystemVerilog USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy. lowRISC/ibex

[2] The public Ibex repository metadata identifies SystemVerilog as the repository language and reports 1,892 stars, 741 forks, and an update time of 2026-05-28T16:04:10Z. lowRISC/ibex

[3] The TestRIG paper lists Ibex among implementations in the TestRIG ecosystem and describes Ibex and Piccolo as simple 32-bit implementations. Randomized Testing of RISC-V CPUs using Direct

[4] TestRIG-compatible implementations use RVFI-DII instrumentation and are expected to provide a common architectural environment including reset behavior and an 8 MiB memory region at address 0x80000000. Randomized Testing of RISC-V CPUs using Direct

[5] The TestRIG repository collates TestRIG-compatible implementations and verification engines and is intended to support standardized RISC-V testing based on instrumentation of open implementations. Randomized Testing of RISC-V CPUs using Direct