A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
PaperFirst seen 6/19/2026
Last seen 6/19/2026
Evidence 13 chunks
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25 connectionsThe paper covers SBST development methods for RISC-V processors.
The paper discusses RISC-V ISA extensions and their role in modular processor design and SBST.
The paper notes that SBST requires no DfT infrastructure and compares RISC-V designs with and without DfT.
The paper uses Chipyard as a key SoC generation framework for SLT research.
The paper covers System-Level Test and how RISC-V supports SLT research.
The paper mentions BOOM as an out-of-order RISC-V core supported by Chipyard.
The paper mentions Ibex as a RISC-V core supported by Chipyard and used in security research.
The paper mentions CV32E40P (RI5CY) as a RISC-V core used as an example for SBST reuse.
The paper mentions CVA6 as an in-order RISC-V core supported by Chipyard.
The paper surveys functional safety mechanisms relevant to RISC-V processors.
The paper discusses side-channel attacks and hardened RISC-V implementations.
The paper discusses dual-core lockstep as a fault tolerance mechanism for RISC-V.
The paper discusses ECC as a functional safety mechanism for RISC-V processors.
The survey paper focuses on RISC-V processors and their testability, safety, and security.
The paper mentions PicoRV32 in the table of selected RISC-V cores.
The paper is co-authored by researchers from University of Freiburg.
The paper is co-authored by researchers from University of Stuttgart.
The paper is co-authored by researchers from Leiden University.
The paper is co-authored by researchers from Universitat Politècnica de València.
Mathias Sauer from Advantest Europe is a co-author of the paper.
The paper covers WCET derivation in the context of RISC-V timing verification for safety.
The paper discusses fault injection as a verification technique for RISC-V safety mechanisms.
The paper mentions the Rocket core as supported by Chipyard.
The paper mentions VexRiscv in the table of selected RISC-V cores.
The paper is co-authored by researchers from Politecnico di Torino.