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STIMSMITH

PicoRV32

Tool
First seen 6/9/2026
Last seen 7/12/2026
Evidence 18 chunks

NEIGHBORHOOD

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RELATIONSHIPS

8 connections
RISC-V implements → 100% 3e
PicoRV32 implements the RISC-V RV32I ISA.
Cascade ← evaluates 100% 2e
Cascade is evaluated on PicoRV32
rtlv: push-button verification of software on hardware ← evaluates 100% 2e
The paper uses PicoRV32 as a motivating example and case study.
Processor Verification using Symbolic Execution: A RISC-V Case-Study ← mentions 85% 2e
The paper mentions PicoRV32 as an example of a RISC-V processor with a native bus interface.
rtlv ← evaluates 100% 2e
rtlv is used to verify deterministic start for the PicoRV32 CPU.
rtlv/shiva ← evaluates 100% 1e
rtlv/shiva was reused to verify output determinism for the PicoRV32 as well.
RISC-V ISA implements → 100% 1e
PicoRV32 is a RISC-V CPU implementation evaluated by Cascade.
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors ← mentions 90% 1e
The paper mentions PicoRV32 in the table of selected RISC-V cores.