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rtlv

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First seen 6/9/2026

Last seen 6/9/2026

Evidence 12 chunks

01

NEIGHBORHOOD

24 nodes · 39 edges

graph · rtlv · depth=1

02

RELATIONSHIPS

23 connections

SymbiYosys compares with → 100% 3e evidence

rtlv is directly compared with SymbiYosys in terms of verification performance.

Rosette uses → 100% 3e evidence

rtlv uses Rosette as its solver-aided programming language for symbolic execution.

microarchitectural state clearing evaluates → 100% 2e evidence

rtlv can verify microarchitectural state clearing properties for processors.

deterministic start evaluates → 100% 2e evidence

rtlv is used to verify the deterministic start property for RISC-V circuits.

output determinism evaluates → 100% 2e evidence

rtlv is used to verify output determinism for MicroTitan SoC.

MicroTitan evaluates → 100% 2e evidence

rtlv is applied to verify the MicroTitan SoC in a case study.

PicoRV32 evaluates → 100% 2e evidence

rtlv is used to verify deterministic start for the PicoRV32 CPU.

rtlv/shiva ← part of 90% 2e evidence

rtlv/shiva is an example property checker that is part of the rtlv framework.

rewrite rules uses → 100% 2e evidence

rtlv benefits from Rosette's rewrite rules to simplify symbolic expressions.

performance hints uses → 100% 2e evidence

rtlv uses performance hints to optimize verification while maintaining correctness.

Racket uses → 95% 2e evidence

rtlv is built on Racket as Rosette is embedded in Racket.

#lang yosys uses → 100% 2e evidence

rtlv uses #lang yosys DSL to transform SMT-LIB circuit models into Rosette code.

hybrid symbolic execution implements → 100% 2e evidence

rtlv implements hybrid symbolic execution as a key technique for efficient verification.

SMT-based formal verification implements → 100% 2e evidence

rtlv implements SMT-based formal verification using Rosette and Z3.

Verilog to Rosette compiler implements → 100% 2e evidence

rtlv includes a Verilog to Rosette compiler as a core component.

circuit-agnostic property checker implements → 100% 2e evidence

rtlv enables development of circuit-agnostic property checkers with a performance hint interface.

sv2v uses → 100% 1e evidence

rtlv uses sv2v to convert SystemVerilog circuits to Verilog before processing.

Yosys uses → 100% 1e evidence

rtlv uses Yosys as its synthesis front-end to produce SMT-LIB circuit representations.

Coq mentions → 90% 1e evidence

rtlv cannot bridge its proofs to Coq for end-to-end metatheory proofs.

push-button formal verification implements → 100% 1e evidence

rtlv implements push-button formal verification of software on hardware.

Verilog uses → 100% 1e evidence

rtlv accepts Verilog as the primary circuit description language.

type-driven state merging uses → 100% 1e evidence

rtlv benefits from Rosette's type-driven state merging to prevent path explosion.

rtlv: push-button verification of software on hardware ← introduces 100% 1e evidence

The paper introduces rtlv as its primary contribution.