#lang yosys

CodeArtifact

First seen 6/9/2026

Last seen 6/9/2026

Evidence 2 chunks

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The paper introduces the #lang yosys DSL as part of the rtlv workflow.

rtlv ← uses 100% 2e

rtlv uses #lang yosys DSL to transform SMT-LIB circuit models into Rosette code.

#lang yosys implements the Verilog to Rosette compilation by transforming Yosys SMT-LIB output.

SMT-LIB uses → 100% 1e

#lang yosys takes Yosys's SMT-LIB output as its input.

Yosys depends on → 100% 1e

#lang yosys depends on Yosys to produce the SMT-LIB circuit representation it transforms.

Rosette depends on → 100% 1e

#lang yosys produces Rosette code that depends on the Rosette language.