Yosys

Tool

First seen 6/6/2026

Last seen 8/15/2026

Evidence 53 chunks

NEIGHBORHOOD

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RELATIONSHIPS

40 connections

ChiGen ← evaluates 100% 5e

ChiGen was used in bug-finding campaigns on Yosys, revealing crashes and issues.

Cascade ← evaluates 100% 3e

Cascade found a critical bug in Yosys synthesizer

Encarsia ← uses 100% 3e

ENCARSIA is implemented as a series of netlist transformation passes in the Yosys Open Synthesis Suite.

RFUZZ ← uses 95% 3e

RFUZZ was adapted using Yosys passes to support Verilog

μARCHIFI ← uses 100% 2e

μARCHIFI is implemented using and integrated into the Yosys toolchain.

RTLIL implements → 100% 2e

Yosys converts HDL designs into RTLIL (RTL Intermediate Language) representations.

multiplexer tree implements → 100% 2e

Yosys transforms conditional assignments into multiplexer trees in its IR.

SymbiYosys ← uses 100% 2e

SymbiYosys uses Yosys's SMT-LIB backend like rtlv.

intermediate representation implements → 100% 2e

Yosys converts HDL designs into an intermediate representation (RTLIL).

ENCARSIA ← uses 100% 2e

ENCARSIA is implemented as a series of netlist transformation passes in Yosys.

μCFI: Formal Verification of Microarchitectural Control-flow Integrity ← uses 95% 2e

The paper uses Yosys passes for static design analysis and taint condition generation.

static design analysis ← uses 90% 2e

Static design analysis in the μCFI toolchain is implemented via Yosys passes.

Verilog uses → 100% 1e

Yosys takes Verilog as input hardware description language.

AIGER uses → 100% 1e

Yosys can produce AIGER output format.

SMV uses → 100% 1e

Yosys can produce SMV output format.

BTOR2 uses → 100% 1e

Yosys can produce BTOR2 output format.

SMT-LIB uses → 100% 1e

Yosys can produce SMT-LIB output format.

Hardware Transition System uses → 100% 1e

Yosys can transform hardware designs into hardware transition systems.

RTL Mutation Engine ← uses 100% 1e

The RTL mutation engine leverages Yosys capabilities to mutate RTL modules.

Mutation Generation Scripts ← uses 95% 1e

The mutation generation scripts use Yosys capabilities for RTL mutation.

rvformal_rand_reg ← uses 93% 1e

The rvformal_rand_reg macro generates Yosys-specific rand reg syntax when YOSYS is defined.

rvformal_rand_const_reg ← uses 93% 1e

The rvformal_rand_const_reg macro generates Yosys-specific rand const reg syntax when YOSYS is defined.

riscv-formal ← uses 95% 1e

riscv-formal supports Yosys as a formal verification backend.

Ibex evaluates → 1e

Yosys is used to synthesize and evaluate the area of Ibex.

Electronic Design Automation ← uses 90% 1e

Yosys is an EDA tool that can benefit from Verilog fuzzers.

Verismith ← evaluates 90% 1e

Verismith was used in bug-finding campaigns on Yosys as a baseline comparison to ChiGen.

VlogHammer ← evaluates 90% 1e

VlogHammer was used in bug-finding campaigns on Yosys as a baseline comparison to ChiGen.

rtlv ← uses 100% 1e

rtlv uses Yosys as its synthesis front-end to produce SMT-LIB circuit representations.

TransFuzz ← evaluates 90% 1e

TransFuzz was used in bug-finding campaigns on Yosys as a baseline comparison to ChiGen.

#lang yosys ← depends on 100% 1e

#lang yosys depends on Yosys to produce the SMT-LIB circuit representation it transforms.

SMT-LIB implements → 100% 1e

Yosys generates SMT-LIB representations of circuits.

Processor Verification ← uses 80% 1e

Yosys is listed among verification tools for RISC-V processors.

FIRRTL uses → 90% 1e

Yosys is used to convert SystemVerilog to FIRRTL for use with DIFUZZRTL.

SystemVerilog HDL uses → 90% 1e

Yosys is used to convert SystemVerilog designs to FIRRTL.

DejaVuzz ← uses 100% 1e

DejaVuzz uses Yosys for diffIFT instrumentation to insert taint cells.

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor ← uses 90% 1e

The paper uses Yosys for synthesis as part of the ATPG-based flow.

ATPG-Based FTBE ← uses 90% 1e

The ATPG-Based FTBE generation uses Yosys for synthesis.

Formal Verification ← uses 93% 1e

Yosys is used as the formal verification framework for property and assumption checking.

Hardware Description Language uses → 100% 1e

Yosys processes hardware designs described in HDLs such as Verilog.

Comparative Evaluation of Open-Source Formal Tools for RISC-V Processor Verification ← evaluates 97% 1e

The paper evaluates Yosys for control logic transition coverage in RISC-V cores, finding it covers only about 35%.