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Yosys

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First seen 6/6/2026

Last seen 6/9/2026

Evidence 6 chunks

01

NEIGHBORHOOD

5 nodes · 7 edges

graph · Yosys · depth=1

02

RELATIONSHIPS

6 connections

SymbiYosys ← uses 100% 2e evidence

SymbiYosys uses Yosys's SMT-LIB backend like rtlv.

rtlv ← uses 100% 1e evidence

rtlv uses Yosys as its synthesis front-end to produce SMT-LIB circuit representations.

#lang yosys ← depends on 100% 1e evidence

#lang yosys depends on Yosys to produce the SMT-LIB circuit representation it transforms.

SMT-LIB implements → 100% 1e evidence

Yosys generates SMT-LIB representations of circuits.

FIRRTL uses → 90% 1e evidence

Yosys is used to convert SystemVerilog to FIRRTL for use with DIFUZZRTL.

SystemVerilog HDL uses → 90% 1e evidence

Yosys is used to convert SystemVerilog designs to FIRRTL.