DejaVuzz
ToolFirst seen 6/13/2026
Last seen 6/13/2026
Evidence 14 chunks
NEIGHBORHOOD
21 nodes · 27 edgesgraph · DejaVuzz · depth=1
RELATIONSHIPS
21 connectionsDejaVuzz introduces taint liveness annotations to bind state registers to related taint registers and filter unexploitable taints.
DejaVuzz addresses microarchitectural controllability by using dynamic swappable memory to resolve address space conflicts.
DejaVuzz supports the RV64GC RISC-V instruction set for stimulus generation.
DejaVuzz designs a taint coverage matrix to guide mutation based on sensitive data propagation.
DejaVuzz checks transient window constant time execution violations as part of its leakage analysis.
DejaVuzz is evaluated on the BOOM RISC-V out-of-order processor.
DejaVuzz is evaluated on the XiangShan RISC-V out-of-order processor.
DejaVuzz uses Yosys for diffIFT instrumentation to insert taint cells.
DejaVuzz uses an ISA simulator to compute operands required to trigger transient windows.
DejaVuzz targets transient execution vulnerabilities as its primary focus.
DejaVuzz treats all register arrays generated by Chisel Vec constructor as potential sinks.
DejaVuzz is designed for and evaluated on transient execution vulnerability detection.
DejaVuzz introduces a mechanism to mitigate control flow over-tainting with acceptable overhead.
DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing ← introduces 100% 1e
The paper introduces DejaVuzz as a novel pre-silicon processor transient execution bug fuzzer.
DejaVuzz introduces the first secret-sensitive coverage matrix designed for transient execution vulnerability fuzzing.
DejaVuzz utilizes dynamic swappable memory as one of its two core operating primitives.
DejaVuzz utilizes differential information flow tracking as one of its two core operating primitives.
DejaVuzz uses the training derivation strategy to derive targeted training based on transient execution information.
DejaVuzz uses the training reduction strategy to eliminate ineffective training and reduce overhead.
DejaVuzz uses RTL simulation to execute generated instruction sequences on the design under test.
DejaVuzz uses Synopsys VCS as the industry-standard RTL simulator for simulation.