XiangShan

Tool

First seen 6/6/2026

Last seen 6/6/2026

Evidence 8 chunks

NEIGHBORHOOD

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DiffTest-H ← evaluates 100% 3e

DiffTest-H is deployed and evaluated on XiangShan, a 6-wide out-of-order RISC-V processor.

RISC-V implements → 100% 3e

XiangShan is a RISC-V processor implementation targeted at the riscv64 ISA.

out-of-order processor implements → 100% 2e

XiangShan is a 6-wide out-of-order processor.

XiangShan supports vector and hypervisor extensions as part of its verification coverage.

DiffTest ← evaluates 97% 1e

Difftest is used to verify the XiangShan processor implementation.

ChiselDB uses → 95% 1e

ChiselDB is integrated into XiangShan for hardware debugging purposes.

TL-Test ← evaluates 90% 1e

TL-Test evaluates the cache subsystem of XiangShan by dumping and replaying traces.

DiffTest uses → 97% 1e

XiangShan uses Difftest for ISA co-simulation based verification.

NEMU uses → 97% 1e

XiangShan uses NEMU as its reference ISA model for architectural state comparison.

LightSSS uses → 88% 1e

XiangShan uses LightSSS for checkpoint-based waveform dumping during simulation.