XiangShan
ToolFirst seen 6/6/2026
Last seen 7/11/2026
Evidence 14 chunks
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
21 connectionsXiangShan is a RISC-V processor design.
DiffTest-H is deployed and evaluated on XiangShan, a 6-wide out-of-order RISC-V processor.
XiangShan supports vector and hypervisor extensions as part of its verification coverage.
DejaVuzz is evaluated on the XiangShan RISC-V out-of-order processor.
XiangShan is a 6-wide out-of-order processor.
XiangShan uses NEMU as the primary golden reference model for differential testing.
scripts/xiangshan.py is part of XiangShan's test execution infrastructure.
XiangShan uses Difftest for ISA co-simulation based verification.
XiangShan employs multi-core validation to verify cache coherence and memory ordering.
XiangShan uses LightSSS for checkpoint-based waveform dumping during simulation.
Difftest is used to verify the XiangShan processor implementation.
XiangShan is a RISC-V out-of-order processor using the RV64GC instruction set.
XSNoCDiffTopConfig is a configuration artifact used in XiangShan multi-core validation.
XiangShan uses the difftest framework for comprehensive functional verification.
XiangShan supports Spike as an alternative golden reference model.
XiangShan supports Verilator as a simulation backend.
XiangShan supports VCS as a simulation backend.
XiangShan implements fork-based checkpointing to accelerate simulation of long-running workloads.
XiangShan supports Profile-Guided Optimization to maximize simulation speed.
ChiselDB is integrated into XiangShan for hardware debugging purposes.
TL-Test evaluates the cache subsystem of XiangShan by dumping and replaying traces.