DiffTest-H
PaperFirst seen 6/6/2026
Last seen 6/6/2026
Evidence 15 chunks
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43 connectionsDiffTest-H is deployed and evaluated on XiangShan, a 6-wide out-of-order RISC-V processor.
DiffTest-H uses register update events as verification events.
DiffTest-H handles MMIO access as a non-deterministic event.
DiffTest-H addresses communication overhead as its primary optimization target.
DiffTest-H optimizes hardware-software communication for co-simulation.
DiffTest-H verifies the design under test by comparing its states against REF.
DiffTest-H uses a golden reference model for comparison against the DUT.
DiffTest-H covers TLB operations as part of its verification event types.
DiffTest-H is evaluated on NutShell, a scalar in-order processor.
DiffTest-H is deployed on Cadence Palladium emulator for hardware-accelerated verification.
DiffTest-H is deployed on Xilinx VU19P FPGA for hardware-accelerated verification.
DiffTest-H is compared against 16-thread Verilator for simulation speed.
DiffTest-H is compared against the Fromajo co-simulation framework on FPGA.
DiffTest-H is compared to the baseline DiffTest framework for speedup.
DiffTest-H is deployed on FPGA for hardware-accelerated co-simulation.
DiffTest-H is deployed on hardware emulator for hardware-accelerated co-simulation.
DiffTest-H uses DPI-C as a hardware-software communication interface.
DiffTest-H uses non-blocking hardware-software parallelism to hide software processing latency.
DiffTest-H processes verification events for co-simulation.
DiffTest-H handles non-deterministic events that must be synchronized to REF.
DiffTest-H uses an ISA checker on the software side to verify DUT correctness.
DiffTest-H uses instruction commit events as verification events from the DUT.
DiffTest-H introduces the Batch technique for tightly packing verification events.
DiffTest-H introduces the Squash technique for order-decoupled event fusion.
DiffTest-H introduces the Replay technique for lightweight debugging.
DiffTest-H is a hardware-accelerated co-simulation framework.
DiffTest-H leverages structural semantics to optimize communication.
DiffTest-H leverages order semantics to decouple communication from checking order.
DiffTest-H uses the LogGP model to analyze hardware-software communication overhead.
Yinan Xu is listed as an author of the DiffTest-H paper.
Kehan Feng is listed as an author of the DiffTest-H paper.
Luoshan Cai is listed as an author of the DiffTest-H paper.
Yaoyang Zhou is listed as an author of the DiffTest-H paper.
Yungang Bao is listed as an author of the DiffTest-H paper.
DiffTest-H uses DUT trace dumping and reloading to support iterative debugging.
DiffTest-H covers cache coherence as one of its verification event types.
DiffTest-H uses Spike as a reference ISS.
DiffTest-H uses NEMU as a reference ISS.
DiffTest-H FPGA platform uses XDMA protocol for hardware-software communication.
DiffTest-H uses GFIFO primitive on Palladium for non-blocking transmission.
DiffTest-H leverages behavioral semantics to enable lightweight debugging.
DiffTest-H is implemented using Chisel HDL.
Kunlin You is listed as an author of the DiffTest-H paper.