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STIMSMITH

Spike (ISS)

Tool
First seen 6/6/2026
Last seen 8/4/2026
Evidence 18 chunks

NEIGHBORHOOD

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RELATIONSHIPS

14 connections
Verification of a RISC-V system with multiple cores ← uses 100% 3e
A modified version of Spike ISS is used as the reference model for co-simulation.
Generic Simulation Testbench ← uses 96% 2e
The testbench compares execution traces against the Spike reference model.
Instruction Set Simulator implements → 100% 2e
Spike is a widely used open-source ISS for RISC-V.
Cascade ← uses 90% 2e
Cascade uses Spike as the ISS for RISC-V program pre-simulation.
CSV-based log comparison scripts ← uses 90% 1e
CSV-based log comparison scripts compare execution logs against Spike ISS reference output.
Understanding UVM Coverage for RISC-V Processor Designs ← uses 100% 1e
Spike ISS is used as the golden reference for checking RTL simulation results.
RISCV-DV testbench ← uses 100% 1e
Spike ISS is run in the RISCV-DV testbench environment to create a golden reference.
riscv-dv ← uses 1e
RISCV-DV supports co-simulation with Spike ISS.
Reusable Verification Environment for a RISC-V Vector Accelerator ← uses 100% 1e
The paper uses Spike as the ISA simulator reference model.
vpu-dv ← uses 100% 1e
vpu-dv uses Spike as the ISA simulator reference model.
DiffTest-H ← uses 85% 1e
DiffTest-H uses Spike as a reference ISS.
Core-UVM environment ← uses 100% 1e
The Core-UVM environment incorporates Spike as a reference model for co-simulation.
UVM environment for RISC-V processors ← mentions 100% 1e
SPIKE is mentioned as a supported ISS for riscv-dv.
Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools ← uses 100% 1e
The paper uses Spike ISS as an open-source reference simulator.