UVM environment for RISC-V processors

Paper

First seen 7/28/2026

Last seen 7/28/2026

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RELATIONSHIPS

34 connections

Reference Model Check uses → 90% 2e

The scoreboard embeds a reference model to check results at runtime.

Corner Case Verification uses → 95% 2e

The paper addresses corner case verification by testing out of normal operating conditions.

UVM Testbench introduces → 95% 2e

The thesis introduces and develops the UVM Testbench for RISC-V verification.

UVM Env Configurator introduces → 90% 2e

The UVM Env Configurator with GUI is introduced in the thesis.

Universal Verification Methodology uses → 100% 2e

The paper uses UVM methodology to build the verification environment.

RV32IMFCXpulp evaluates → 100% 2e

The thesis develops a verification environment to verify the RV32IMFCXpulp processor.

RI5CY Processor evaluates → 100% 2e

The paper verifies the RI5CY processor (RV32IMFCXpulp).

Coverage-Driven Verification uses → 95% 1e

The paper employs Coverage Driven Verification as part of the UVM framework.

Code Coverage uses → 100% 1e

The paper uses Code Coverage with its metrics to track verification improvements.

Fault Injection uses → 100% 1e

The paper uses fault injection (illegal instructions, interrupts, resets) to test corner cases.

Illegal Instruction Injection uses → 100% 1e

Illegal instructions are injected as part of fault injection to test error detection logic.

Random Constrained Stimulus Generation uses → 100% 1e

Python scripts are used to generate random constrained stimuli according to the ISA.

Python Script uses → 100% 1e

Python scripts generate random constrained stimuli and extract simulation results.

RVGEN2.py introduces → 90% 1e

RVGEN2.py is a Python tool introduced in this thesis to generate random programs.

RV Generator introduces → 90% 1e

The RV Generator is introduced as part of the simulation environment.

ISA Database introduces → 90% 1e

The ISA Database is introduced as part of the simulation environment.

riscv-dv mentions → 100% 1e

riscv-dv is mentioned as a related state-of-the-art UVM-based RISC-V verification tool.

Processor-UVM-Verification mentions → 100% 1e

Processor-UVM-Verification by Anish Gupta is mentioned as the starting point of the thesis.

Spike (ISS) mentions → 100% 1e

SPIKE is mentioned as a supported ISS for riscv-dv.

Imperas OVPsim mentions → 100% 1e

Imperas OVPsim is mentioned as a supported ISS for riscv-dv.

Western Digital Whisper ISS mentions → 100% 1e

Western Digital Whisper is mentioned as a supported ISS for riscv-dv.

SAIL_RISCV ISS mentions → 100% 1e

SAIL_RISCV is mentioned as a supported ISS for riscv-dv.

Instruction Set Coverage uses → 95% 1e

Instruction Set Coverage is used as a coverage metric in the simulation results.

statement coverage uses → 95% 1e

Statement coverage is one of the code coverage metrics used.

expression coverage uses → 95% 1e

Expression coverage is one of the code coverage metrics used.

FSM coverage uses → 95% 1e

FSM coverage is one of the code coverage metrics used.

Interrupt Request Injection uses → 100% 1e

Interrupt requests are injected as part of the verification strategy.

Transaction Level Modeling uses → 90% 1e

UVM uses TLM APIs to facilitate inter-communication between UVM components.

Asynchronous Reset Injection uses → 100% 1e

Asynchronous resets are injected as part of the verification strategy.

Leonardo Barraco authored by → 100% 1e

Leonardo Barraco is the candidate/author of the thesis.

Edgar Ernesto Sanchez Sanchez authored by → 90% 1e

Edgar Ernesto Sanchez Sanchez is the advisor of the thesis.

Annachiara Ruospo authored by → 90% 1e

Annachiara Ruospo is a co-advisor of the thesis.

Politecnico di Torino published by → 100% 1e

The thesis was produced at Politecnico di Torino.

Simulation-Based Verification uses → 100% 1e

The paper develops a simulation-based verification environment.