UVM Testbench

Tool

First seen 7/19/2026

Last seen 7/28/2026

Evidence 4 chunks

NEIGHBORHOOD

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12 connections

The thesis introduces and develops the UVM Testbench for RISC-V verification.

UVM scoreboard ← part of 100% 2e

The UVM Testbench includes a Scoreboard for checking results.

The UVM Testbench implements the Universal Verification Methodology.

UVM agent ← part of 100% 1e

The UVM Testbench contains UVM Agents as main components.

UVM Monitor ← part of 100% 1e

The UVM Testbench includes monitors for capturing transactions.

UVM Sequence ← part of 100% 1e

The UVM Testbench includes sequences for stimulus generation.

Interfaces are defined in processor_interface.sv and used by UVM components.

Interfaces are defined in processor_interface_out.sv and used by UVM components.

riscv_core.sv evaluates → 100% 1e

The UVM Testbench verifies the riscv_core.sv RTL implementation.

RISC-V CPU Verification uses an open-source UVM testbench for practical exercises.

data_ram.sv uses → 100% 1e

data_ram.sv is encapsulated in the wrapper along with riscv_core.sv.

UVM implements → 95% 1e

The UVM Testbench is an implementation of the UVM (Universal Verification Methodology) standard.