Coverage-Driven Verification

Concept

Coverage-driven verification is a hardware verification approach that organizes simulation-based testing around coverage metrics and coverage goals. In the provided evidence it is closely tied to functional coverage, UVM/SystemVerilog testbenches, constrained-random or direct test sequences, and feedback techniques for automated coverage closure.

First seen 5/24/2026

Last seen 5/28/2026

Evidence 9 chunks

Wiki v4

WIKI

Coverage-Driven Verification

Coverage-driven verification is a hardware verification approach in which the verification process is guided by coverage metrics and coverage goals. In the provided UVM-based RISC-V evidence, simulation-based verification is described as a central part of the verification plan, and coverage metrics are used to determine whether a sufficient portion of the design under test (DUT) has been exercised.^[1]

Coverage metrics

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NEIGHBORHOOD

2 nodes · 1 edges

graph · Coverage-Driven Verification · depth=1

RELATIONSHIPS

4 connections

Functional Coverage uses → 90% 2e

Coverage-driven verification uses functional coverage metrics to guide verification.

UVM Based Design Verification of a RISC-V CPU Core ← uses 100% 1e

The paper employs coverage-driven verification enabled by UVM and SystemVerilog.

CPU Verification ← uses 85% 1e

CPU verification uses coverage-driven verification approaches.

UVM ← implements 90% 1e

UVM implements coverage-driven verification as a standard methodology for reusable testbench structures.

LINKED ENTITIES

2 links

UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship

Functional Coverage PART_OF Extracted graph relationship

CITATIONS

10 sources

10 citations — click to expand

[1] Coverage-driven verification is guided by coverage metrics and coverage goals within simulation-based verification plans. [PDF] UVM-based verification of RISC-V superscalar processors

[2] Structural coverage includes code, toggle, branch, and FSM coverage and is automatically measured during simulation. [PDF] UVM-based verification of RISC-V superscalar processors

[3] Functional coverage is user-specified, targets semantic aspects of the design, counts architecturally interesting events, and helps determine whether requirements and scenarios have been tested. [PDF] UVM-based verification of RISC-V superscalar processors

[4] A UVM-style testbench uses sequence generators, drivers, monitors, and scoreboards to generate stimulus and check observed DUT behavior against expected behavior. [PDF] UVM-based verification of RISC-V superscalar processors

[5] SystemVerilog provides constructs for testbenches, functional coverage, and assertions, including covergroups, coverpoints, sequences, properties, assertions, and cover statements. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] Coverage-closure automation can be framed as choosing among direct or parameterized constrained-random sequences to maximize functional coverage over multiple trials. [PDF] UVM-based verification of RISC-V superscalar processors

[7] Automation is identified as useful both for creating functional coverage models and for applying tests to achieve autonomous coverage closure with small regression-test time. [PDF] UVM-based verification of RISC-V superscalar processors

[8] Reported feedback-directed techniques include RNN-based constraint adjustment, feedback-adjusted Markov models, and reseeding with checkpoint rollback. [PDF] UVM-based verification of RISC-V superscalar processors

[9] The Takakis thesis proposes multi-armed-bandit and feedback-based mechanisms to increase functional coverage and decrease test-application time for a 2-way superscalar out-of-order RISC-V processor. [PDF] UVM-based verification of RISC-V superscalar processors

[10] The Occhineri RISC-V CPU verification source describes UVM as a SystemVerilog-based standardized methodology for reusable testbenches with drivers, monitors, stimulus generators, and scoreboards. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi