Coverage-Driven Verification

Technique

Coverage-Driven Verification is an iterative verification technique in which functional and stimulus coverage results guide test generation, debug, and targeted closure. In the provided RISC-V verification evidence, the flow combines constrained-random stimulus, directed test suites, generated SystemVerilog coverage models, reference-model comparison, and deterministic replay to expose coverage gaps and close them.

First seen 5/25/2026

Last seen 7/6/2026

Evidence 16 chunks

Wiki v1

WIKI

Overview

Coverage-Driven Verification is an iterative technique that uses measured coverage results to decide what to test next. In the RISC-V verification flow described in the evidence, coverage closure is defined as achieving sufficient functional and code coverage to provide confidence that relevant design behaviours have been tested. Functional Coverage and Stimulus Coverage measure how thoroughly stimulus has exercised ISA features and system behaviours, and automatically generated coverage models can provide detailed insight into coverage gaps.

Core idea

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RELATIONSHIPS

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Processor Verification ← uses 93% 2e

Coverage-driven verification is used to measure completeness of processor verification.

Functional Coverage uses → 95% 2e

Coverage-driven verification employs functional coverage to measure and close coverage gaps.

Functional Coverage uses → 97% 2e

Coverage-Driven Verification uses functional coverage to measure how much of the design has been tested.

Automation of Processor Verification Using Recurrent Neural Networks ← uses 90% 2e

The paper monitors coverage to determine verification completeness, which is characteristic of coverage-driven verification.

Covergroup uses → 93% 1e

Coverage-Driven Verification uses covergroups to define and collect functional coverage data.

Directed-Random Verification implements → 90% 1e

Coverage-Driven Verification implements Directed-Random Verification by using coverage data to direct test generation.

Constrained-Random Stimulus Generation uses → 94% 1e

Coverage-driven verification uses constrained-random stimulus generation to exercise the DUT.

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Functional Coverage USES Extracted graph relationship

Stimulus Coverage USES Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Coverage closure is the process of achieving sufficient functional and code coverage to provide confidence that relevant design behaviours have been tested. source

[2] Functional Coverage and Stimulus Coverage measure how thoroughly stimulus has exercised ISA features and system behaviours. source

[3] A hybrid RISC-V verification flow combines constrained-random sweeps with functional coverage analysis using ImperasFC. source

[4] ImperasFC generates SystemVerilog coverage models directly from the ISA specification, and the resulting functional coverage can be viewed in standard coverage reporting tools such as Verdi. source

[5] Coverage analysis can begin before RTL using ImperasSC, supporting a shift-left verification approach. source

[6] Directed suites such as TS-ISA, TS-VECT, TS-MMU, PMP, and ePMP target architectural validation, vector extensions, virtual memory, and protection features. source

[7] Directed suites can close gaps left by random stimulus; the evidence describes TS-MMU tests exposing a TLB flush ordering issue after weak Sv39 and Sv48 page-table-walk coverage was identified. source

[8] The described flow integrates simulation, reference-model lock-step comparison, debug, emulation, prototyping, and deterministic replay. source

[9] The evidence lists faster coverage closure, improved debug efficiency, scalability and reproducibility, portability, and future-ready compliance as benefits of the hybrid approach. source