Functional Coverage

Technique

First seen 7/6/2026

Last seen 8/28/2026

Evidence 11 chunks

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Functional coverage measures whether semantically distinct situations for the custom instruction have been exercised.

Functional coverage includes register aliasing as a coverage dimension.

Coverage-driven verification employs functional coverage to measure and close coverage gaps.

RISC-V evaluates → 95% 2e

Functional coverage is used to ensure thorough verification of RISC-V instruction execution.

Functional coverage includes exception scenarios as a required coverage dimension.

Alpinum Consulting ← mentions 90% 2e

Alpinum Consulting provides a guide on functional coverage for RISC-V verification.

Functional coverage includes privilege mode as a coverage dimension.

SystemVerilog uses → 95% 1e

Functional coverage is implemented using SystemVerilog covergroups and coverpoints

UVM Monitor ← uses 93% 1e

The UVM monitor implements covergroups to track functional coverage.

Functional coverage is one of the ASIC/SoC DV techniques applicable to RISC-V design verification

riscvISACOV ← implements 95% 1e

riscvISACOV is a functional coverage tool for RISC-V ISA

Imperas RVFCgen ← implements 95% 1e

Imperas RVFCgen generates SystemVerilog functional coverage source files from machine-readable ISA definitions

The thesis uses coverage collection as part of the UVM infrastructure.

XLEN uses → 88% 1e

Functional coverage includes XLEN configuration variants as a coverage dimension.