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STIMSMITH

Functional Coverage

Technique
First seen 7/6/2026
Last seen 8/28/2026
Evidence 11 chunks

NEIGHBORHOOD

1 nodes · 0 edges
graph · Functional Coverage · depth=1

RELATIONSHIPS

14 connections
custom RISC-V instruction evaluates → 95% 3e
Functional coverage measures whether semantically distinct situations for the custom instruction have been exercised.
register aliasing uses → 90% 2e
Functional coverage includes register aliasing as a coverage dimension.
Coverage-Driven Verification ← uses 95% 2e
Coverage-driven verification employs functional coverage to measure and close coverage gaps.
RISC-V evaluates → 95% 2e
Functional coverage is used to ensure thorough verification of RISC-V instruction execution.
exception and trap behaviour uses → 90% 2e
Functional coverage includes exception scenarios as a required coverage dimension.
Alpinum Consulting ← mentions 90% 2e
Alpinum Consulting provides a guide on functional coverage for RISC-V verification.
privilege mode verification uses → 90% 2e
Functional coverage includes privilege mode as a coverage dimension.
SystemVerilog uses → 95% 1e
Functional coverage is implemented using SystemVerilog covergroups and coverpoints
UVM Monitor ← uses 93% 1e
The UVM monitor implements covergroups to track functional coverage.
RISC-V Design Verification part of → 95% 1e
Functional coverage is one of the ASIC/SoC DV techniques applicable to RISC-V design verification
riscvISACOV ← implements 95% 1e
riscvISACOV is a functional coverage tool for RISC-V ISA
Imperas RVFCgen ← implements 95% 1e
Imperas RVFCgen generates SystemVerilog functional coverage source files from machine-readable ISA definitions
RISC-V UVM Verification Thesis ← uses 95% 1e
The thesis uses coverage collection as part of the UVM infrastructure.
XLEN uses → 88% 1e
Functional coverage includes XLEN configuration variants as a coverage dimension.