SystemVerilog

Concept

SystemVerilog is a hardware description language used in RTL design, verification, and code-generation research. The supplied evidence highlights its role in Google’s RISC-V Design Verification framework, where constraint-based SystemVerilog specifications generate RISC-V assembly tests, and in RISC-V implementation ecosystems such as TestRIG, where implementations may be written in SystemVerilog or Bluespec. Recent research also treats SystemVerilog as both an interoperability target for newer HDLs such as Veryl and a challenging target for LLM-based HDL generation because correct generated code must satisfy timing, concurrency, and synthesizability constraints.

First seen 5/25/2026

Last seen 6/9/2026

Evidence 26 chunks

Wiki v5

WIKI

SystemVerilog

Overview

SystemVerilog is described in the supplied public research context as a hardware description language (HDL). Recent work on HDL generation treats SystemVerilog as a target for synthesizable and functionally accurate implementations, and notes that HDL code generation must handle strict timing semantics, concurrency, and synthesizability constraints.[systemverilog-hdl-generation-challenges]

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NEIGHBORHOOD

2 nodes · 1 edges

graph · SystemVerilog · depth=1

RELATIONSHIPS

15 connections

riscv-dv ← uses 100% 5e

RISC-V DV uses SystemVerilog for its constraint-based test generator.

RISC-V Design Verification (DV) Framework ← uses 100% 2e

RISC-V DV uses SystemVerilog for constraint-based specification.

DPI Interface uses → 95% 2e

SystemVerilog testbenches interface with system-level via the DPI layer.

eUVM compares with → 100% 2e

eUVM is compared with SystemVerilog UVM achieving over 100x speedup.

UVM Based Design Verification of a RISC-V CPU Core ← uses 100% 1e

The paper uses SystemVerilog for the verification infrastructure.

Core-V-Verif ← uses 95% 1e

Core-V-Verif uses class libraries based on SystemVerilog.

UVM ← uses 95% 1e

UVM is a class library defined using the syntax and semantics of SystemVerilog.

Random Instruction Generator ← uses 90% 1e

The RIG uses SystemVerilog constraints for random instruction generation.

Ibex ← uses 85% 1e

Ibex is written in SystemVerilog.

rvfi_testbench.sv ← implements 97% 1e

rvfi_testbench.sv is a SystemVerilog file

cover_stmts.vh ← implements 93% 1e

cover_stmts.vh contains SystemVerilog cover() statements

cover check ← uses 97% 1e

Cover checks use SystemVerilog cover() statements

Google RISC-V Design Verification (DV) Framework ← uses 95% 1e

Google DV framework uses SystemVerilog for its constraint-based specifications.

riscv-dv ← implements 1e

RISCV-DV is implemented using SystemVerilog.

sv2v ← implements 100% 1e

sv2v converts SystemVerilog to Verilog.

LINKED ENTITIES

1 links

Google RISC-V Design Verification (DV) Framework USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] systemverilog-hdl-generation-challenges ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols

[2] veryl-systemverilog-interoperability Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog

[3] riscv-dv-systemverilog Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[4] riscv-dv-cosimulation Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[5] riscv-dv-limitations Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[6] testrig-riscv-implementations Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[7] testrig-rvfi-dii Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[8] protocollm-systemverilog-benchmark ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols