Coverage-Driven Verification

Technique

Coverage-Driven Verification (CDV) is an iterative hardware verification methodology that uses a verification plan, constrained-random test generation directed by test-templates, and coverage feedback to guide the verification process toward coverage closure. Originating in processor verification (Abarbanel et al., 1996), it has been extended to unify pre-silicon simulation and post-silicon silicon validation (Adir et al., DATE 2011), underpins modern RISC-V UVM flows, supports Chisel-built processor models via staged strategies, and is being enhanced with machine-learning techniques to reduce redundant regression simulation.

First seen 5/25/2026

Last seen 9/3/2026

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Overview

Coverage-Driven Verification (CDV) is a functional verification methodology in which a verification plan specifies the features to be checked, constrained-random stimuli are directed toward those goals via test-templates, and coverage analysis provides feedback that drives subsequent stimulus and test-template changes. The IBM DATE 2011 unified methodology paper (Adir et al.) describes CDV as being "based on three main components": a verification plan of features in the Design Under Verification (DUV), random stimuli generators directed toward those goals via test-templates, and coverage analysis tools that detect verification-plan events and report progress.

The same paper traces CDV back to established prior work on test-generation and coverage-driven classification, citing Abarbanel, Lichtenstein, Malka and Ur's "Coverage Driven Processor Bug Classification" (submitted to DAC 1996) as a foundational reference for the methodology. CDV draws on earlier work in protocol design validation (Holtzman 1991), symbolic model checking (McMillan 1992/1993), symbolic instruction-graph architectural verification (Chandra et al. 1994), constraint-based test-program generation (Lewin et al. 1995; Chandra and Iyengar 1992), architectural validation (Ho et al. 1995), and automatic test-program generation for pipelined processors (Iwashita et al. 1994).

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NEIGHBORHOOD

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graph · Coverage-Driven Verification · depth=1

RELATIONSHIPS

14 connections

Functional Coverage uses → 100% 3e

CDV uses coverage analysis to detect events and provide verification feedback.

Functional Coverage uses → 95% 2e

Coverage-driven verification employs functional coverage to measure and close coverage gaps.

Processor Verification ← uses 93% 2e

Coverage-driven verification is used to measure completeness of processor verification.

Automation of Processor Verification Using Recurrent Neural Networks ← uses 90% 2e

The paper monitors coverage to determine verification completeness, which is characteristic of coverage-driven verification.

A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation ← uses 100% 1e

The methodology extends coverage-driven verification to the post-silicon domain.

Verification Plan uses → 100% 1e

CDV is based on a verification plan comprising features in the DUV.

Test Template uses → 100% 1e

CDV uses test-templates to direct random stimuli generators.

Random Stimuli Generation uses → 100% 1e

CDV relies on random stimuli generators as one of its three main components.

Coverage Driven Processor Bug Classification ← uses 100% 1e

The paper uses coverage-driven verification for processor bug classification.

Research on functional verification method processor model built by Chisel ← uses 95% 1e

The paper uses coverage-driven verification as one of its verification stages.

Universal Verification Methodology (UVM) part of → 90% 1e

Coverage-driven verification is a primary advantage of UVM methodology.

Covergroup uses → 93% 1e

Coverage-Driven Verification uses covergroups to define and collect functional coverage data.

Directed-Random Verification implements → 90% 1e

Coverage-Driven Verification implements Directed-Random Verification by using coverage data to direct test generation.

Constrained-Random Stimulus Generation uses → 94% 1e

Coverage-driven verification uses constrained-random stimulus generation to exercise the DUT.

LINKED ENTITIES

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Research on functional verification method processor model built by Chisel USES Extracted graph relationship

A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation EXTENDS The Adir et al. DATE 2011 paper extends CDV to a unified pre-/post-silicon methodology with shared verification plans, test-templates, and coverage models, introducing Threadmill.

Coverage Driven Processor Bug Classification FOUNDATIONAL_REFERENCE Adir et al. cite Abarbanel et al. (DAC 1996) as the foundational reference for CDV's coverage-driven classification approach.

CITATIONS

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10 citations — click to expand

[1] CDV is based on three main components: a verification plan of DUV features, random stimuli generators directed by test-templates, and coverage analysis tools that detect verification-plan events and report progress. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation (Adir et al., DATE 2011)

[2] Test-templates focus random generators on areas ranging from generic (e.g., a floating-point unit) to specific (e.g., a bypass between pipeline stages), and coverage analysis identifies gaps used to modify or create test-templates. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation (Adir et al., DATE 2011)

[3] Post-silicon observability is limited, so coverage is measured on the acceleration platform and a regression suite of exerciser test-templates is created based on accelerator-achieved coverage to continue verification on silicon. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation (Adir et al., DATE 2011)

[4] Threadmill is a post-silicon exerciser built to the same verification-plan/test-template/coverage-model conventions, taking as inputs the test-template, an architectural model with testing knowledge, and the system topology; a builder application creates an executable exerciser image composed of an OS-like service layer, the template/model representation, and generator logic. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation (Adir et al., DATE 2011)

[5] Abarbanel, Lichtenstein, Malka and Ur's 'Coverage Driven Processor Bug Classification' (DAC 1996) is cited as the foundational reference for CDV. A methodology for processor implementation verification (Springer Nature)

[6] The OpenHW-style RISC-V toolchain uses 'smart' random instruction generators with manually set generation parameters, exemplified by RISCV-DV (SV/UVM-based, RV32IMAFDC/RV64IMAFDC, multiple privilege modes, PyVSC), FORCE-RISCV (OpenHW Group, Python API, RV32G/RV64G, V extension, U/S/M privilege, Sv32/Sv39/Sv48, embedded ISS), and riscvISACOV (Imperas-led OpenHW ARVM-Functional Coverage shared coverage infrastructure). Reinforcement Learning Framework for RISC-V Functional Verification (Politecnico di Torino thesis)

[7] UVM-based RISC-V core-block verification follows a coverage-driven loop: develop constrained-random and directed sequences, drive them into the DUT through UVM drivers, capture DUT activity in monitors with covergroups, add SystemVerilog assertions for protocol and corner-case checks, then perform coverage analysis and regression to close gaps. Verification Of Risc-V Core Blocks Using Uvm (IJEDR 2025)

[8] Traditional CDV and constrained-random verification rely on time-consuming and redundant simulation regression, with manual effort to adjust constraints and drive stimuli toward coverage objectives, motivating ML-based optimisations that can achieve at least 99% coverage regain with significantly reduced simulation cycles. Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM (arXiv, 2025)

[9] Supervised learning (scikit-learn algorithms) can optimise CDV simulation regressions, recovering at least 99% coverage with significantly reduced simulation cycles; PyUVM is used over SV-UVM to simplify testbench construction and reuse ML libraries; results are demonstrated across three diverse designs. Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM (arXiv, 2025)

[10] For a Chisel-built ARM V4-compatible processor model (ARMChisel), a four-stage CDV strategy is proposed: Chisel-level primary verification, rapid coverage verification, directed test verification, and complex-application verification, with FPGA acceleration for large applications and Chisel+Verilog testbenches that collect coverage while detecting and locating errors. Research on functional verification method processor model built by Chisel (JNWPU 2023)