Overview
Coverage-Driven Verification is an iterative technique that uses measured coverage results to decide what to test next. In the RISC-V verification flow described in the evidence, coverage closure is defined as achieving sufficient functional and code coverage to provide confidence that relevant design behaviours have been tested. Functional Coverage and Stimulus Coverage measure how thoroughly stimulus has exercised ISA features and system behaviours, and automatically generated coverage models can provide detailed insight into coverage gaps.
Core idea
The technique is based on a feedback loop:
- Generate broad tests, such as constrained-random stimulus.
- Measure coverage using functional and stimulus coverage models.
- Identify gaps in ISA features, system behaviours, or specific architectural areas.
- Add directed tests or targeted suites to exercise the missing behaviours.
- Merge results, debug failures, and replay failing cases deterministically.
The evidence describes a hybrid flow for RISC-V in which constrained-random sweeps are followed by functional coverage analysis. Coverage gaps are then highlighted and closed, with results merged in Verdi and failing cases replayed deterministically in VCS.
Coverage inputs
Functional Coverage
Functional Coverage is used to measure how thoroughly the stimulus has exercised ISA features and system behaviours. The evidence states that ImperasFC can generate SystemVerilog coverage models directly from the ISA specification. Because the generated functional coverage is conventional SystemVerilog, results can be viewed in a standard coverage reporting tool such as Verdi, and users can extend the models for custom features and cross-coverage points.
Stimulus Coverage
Stimulus Coverage is also used to assess how thoroughly generated tests exercise ISA features and system behaviours. The evidence states that coverage analysis can begin before RTL using ImperasSC, enabling a shift-left approach in which validation starts earlier in the flow.
Hybrid closure flow
The provided evidence emphasizes that the most effective strategy combines constrained-random and directed tests. A typical flow begins with constrained-random sweeps using STING, then applies functional coverage analysis using ImperasFC. Where coverage gaps remain, directed suites such as TS-ISA, TS-VECT, TS-MMU, PMP, and ePMP can be used to target architectural features and protection mechanisms.
Directed suites are described as efficient for areas where random stimulus often leaves gaps. One example in the evidence notes that coverage analysis revealed weak points in Sv39 and Sv48 page-table walks, and adding TS-MMU tests exposed a subtle ordering issue in TLB flush logic.
Debug and integration
Coverage-driven closure is integrated with simulation, reference models, debug tools, and hardware-assisted platforms in the described RISC-V flow. Constrained-random programs can run in simulators such as VCS, while Verdi provides centralized debug. ImperasDV enables lock-step comparison against a reference model at instruction retirement, helping catch errors early. The same stimulus can be reused in ZeBu emulation or HAPS prototyping, extending validation to system-level workloads.
Benefits described in the evidence
The evidence identifies several benefits of a hybrid coverage-driven flow for RISC-V verification teams:
- Faster coverage closure by combining random stimulus with directed suites.
- Improved debug efficiency through self-checking tests and lock-step compare.
- Scalability and reproducibility using logged seeds and directed reruns.
- Portability across simulation, emulation, FPGA prototyping, and silicon.
- Earlier validation through pre-RTL stimulus coverage analysis.