RISC-V UVM Verification Thesis

Paper

First seen 7/6/2026

Last seen 7/6/2026

Evidence 1 chunks

NEIGHBORHOOD

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6 connections

The thesis integrates Spike as a reference ISA model for RISC-V verification.

The thesis uses random instruction generators as part of its verification flow.

Directed Testing uses → 96% 1e

The thesis includes directed tests in its verification infrastructure.

The thesis uses coverage collection as part of the UVM infrastructure.

UVM uses → 98% 1e

The thesis describes a full UVM infrastructure for RISC-V verification.

RISC-V evaluates → 97% 1e

The thesis targets RISC-V processor verification.