Random Instruction Generator

CodeArtifact

The Random Instruction Generator (RIG) is a constrained generator used in the top-level verification of a RISC-V superscalar processor. It produces valid, ISA-compliant assembly instruction sequences, supports both instruction-level and sequence-level randomization, and can be tuned through parameters for instruction mix, hazards, memory dependencies, loops, and branches.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

The Random Instruction Generator (RIG) is a verification code artifact used to generate instruction sequences for the top-level verification of a full RISC-V processor. In the cited RISC-V verification flow, the device under verification is a two-way superscalar out-of-order microprocessor implementing the RISC-V ISA, and top-level tests interact with the processor through assembly-language instruction sequences. The RIG was developed together with an Instruction Set Simulator (ISS) to help exercise architectural features of the processor, including rarely encountered corner cases. ^[1] ^[2]

Purpose in verification

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RELATIONSHIPS

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RISC-V uses → 95% 2e

The random instruction generator is designed for RISC-V processors.

Constrained Random Verification uses → 90% 2e

The random instruction generator uses constrained randomization to generate instruction sequences.

SystemVerilog uses → 90% 1e

The RIG uses SystemVerilog constraints for random instruction generation.

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CITATIONS

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[1] The RIG was used for top-level verification of a RISC-V superscalar out-of-order processor, together with an ISS, to generate instruction sequences that exercise architectural features and corner cases. [PDF] UVM-based verification of RISC-V superscalar processors

[2] At top-level verification, test sequences take the form of valid, ISA-compliant assembly-language instruction sequences executed on the processor. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The RIG supports instruction-level randomization and sequence-level randomization for operands, immediates, ordering, and dependencies. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The RIG is parameterized by instruction mix, dependency rates, memory dependency rate, loop rates, nested-loop rate, and forward-branch rate. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The RIG outputs a little-endian hex file positioned in memory and an assembly file with corresponding memory addresses. [PDF] UVM-based verification of RISC-V superscalar processors

[6] For load/store generation, the RIG emits setup instructions and uses SystemVerilog randomization constraints to keep generated addresses within valid data memory, aligned, and non-negative under sign extension. [PDF] UVM-based verification of RISC-V superscalar processors

[7] The RIG can generate for-loop constructs containing an iteration counter, random loop-body instructions, a flag register, and a backward branch. [PDF] UVM-based verification of RISC-V superscalar processors

[8] The RIG can generate both generic and directed test instruction sequences by adjusting parameters, and it also provides an interface for handwritten assembly. [PDF] UVM-based verification of RISC-V superscalar processors