Asynchronous Reset Injection

Concept

Asynchronous Reset Injection is a functional verification technique in which reset signals are deliberately applied to a processor outside of normal operating conditions, in order to stress reset behavior and reach higher coverage during simulation-based verification.

First seen 7/28/2026

Last seen 7/28/2026

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Asynchronous Reset Injection

Asynchronous Reset Injection is a verification technique used during the simulation-based functional verification of processors such as the RISC-V RV32IMFCXpulp core. It belongs to the broader category of Fault Injection, since it deliberately perturbs the Design Under Verification (DUV) with out-of-normal-condition stimuli to expose corner-case behavior.

Purpose

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RELATIONSHIPS

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UVM environment for RISC-V processors ← uses 100% 1e

Asynchronous resets are injected as part of the verification strategy.

Fault Injection part of → 90% 1e

Asynchronous reset injection is a type of fault injection used in the thesis.

LINKED ENTITIES

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UVM environment for RISC-V processors USES Extracted graph relationship

Fault Injection PART_OF Extracted graph relationship

CITATIONS

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[1] Asynchronous reset injection is one of the abnormal-condition stimuli used to reach high code coverage during UVM-based verification of the RISC-V RV32IMFCXpulp processor. UVM environment for RISC-V processors

[2] A 90.1% coverage level was reached by injecting test vectors including illegal instructions (Fault Injection), interrupt requests, and asynchronous resets. UVM environment for RISC-V processors