Simulation-Based Verification
TechniqueSimulation-based verification is a hardware-verification technique in which generated stimuli are run on a design under verification and the resulting behavior and coverage are observed. In the provided evidence, it is commonly discussed for processor and RISC-V verification, where constrained-random or pseudorandom instruction generation, functional-coverage feedback, reference-model comparison, coverage-directed test selection, and novelty-driven verification are used to improve verification efficiency. The evidence also emphasizes that simulation alone is inadequate for complex processors and is typically complemented by formal methods, hardware-assisted validation, and operational software testing.
First seen 5/25/2026
Last seen 6/6/2026
Evidence 12 chunks
Wiki v4
WIKI
Overview
Simulation-based verification applies generated stimuli to a design under verification and observes the resulting behavior and coverage. In processor verification, one described trend is to generate stimuli using pseudorandom generators, apply those stimuli to processor inputs, and monitor functional coverage to assess verification completeness. The stimuli may be raw bit vectors applied to input ports or programs loaded into program memory. [C1]
Constrained random test generation is described as one of the most widely adopted methods for generating stimuli for simulation-based verification. Randomness provides test diversity, but tests can repeatedly exercise the same design logic, so constraints are typically written to bias tests toward interesting, hard-to-reach, or not-yet-tested logic. Several millions of tests may be required to achieve coverage goals with constrained random test generation, and the vast majority of tests do not contribute to coverage progress yet still consume verification resources. [C2]
NEIGHBORHOOD
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9 connectionsThe paper addresses testing in the context of simulation-based hardware verification.
Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← uses 100% 3e
The paper addresses test selection within the context of simulation-based verification.
Static formal verification and simulation-based verification are compared as two main methods for hardware bug discovery.
Simulation-based verification is used to validate processor designs and produce coverage reports.
The paper operates in the context of simulation-based verification of processors.
Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← evaluates 90% 1e
The paper evaluates coverage-directed test selection within the context of simulation-based verification.
Simulation-based verification uses RTL simulation to translate and execute hardware designs.
Simulation-based verification uses a golden reference model to check DUT correctness.
The paper uses simulation-based verification as its primary methodology.
LINKED ENTITIES
3 linksSupervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification USES Extracted graph relationship
Hybrid Intelligent Testing in Simulation-Based Verification USES This paper, explicitly supported by the provided evidence, combines coverage-directed test selection and novelty-driven verification within simulation-based verification, and is discussed in the Novelty-driven verification and hybrid intelligent testing section.
Automation of Processor Verification Using Recurrent Neural Networks USES This paper, explicitly supported by the provided evidence, applies simulation-based verification to processor designs using pseudorandom generators and a recurrent-neural-network-based coverage feedback loop, and is discussed in the Stimulus generation and coverage feedback section.
CITATIONS
17 sources17 citations — click to expand
[1] Current trend in processor simulation-based verification uses pseudorandom generators to generate stimuli applied to processor inputs while monitoring functional coverage; stimuli can be bit vectors on input ports or programs loaded into program memory. Automation of Processor Verification Using Recurrent Neural Networks
[2] Constrained random test generation is one of the most widely adopted stimulus-generation methods for simulation-based verification; constraints are written to bias tests toward interesting, hard-to-reach, and yet-untested logic, but several millions of tests may be required for coverage goals and the vast majority do not contribute to coverage progress. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[3] Processor verification challenges lie in the microarchitecture and pipeline; SystemVerilog and UVM are common but coverage is limited because claiming 100% coverage for an instruction such as `add` does not imply coverage of all operand and microarchitectural combinations. RISC-V Microarchitecture Verification Approaches
[4] Simulation is necessary in a hybrid processor-verification strategy to validate all modules of a large processor, check SoC integration, and run software on the device under test; most teams validate by comparing implemented behavior with a reference model, and when they differ, engineers must judge whether the RTL behavior is acceptable. RISC-V Microarchitecture Verification Approaches
[5] RISC-V custom instructions and added features require re-verification of impacted functionality and checks that the changes do not negatively affect the rest of the design, especially when they affect pipeline control, ALU conflicts, cache behavior, or load-store paths. RISC-V Microarchitecture Verification Approaches
[6] A recurrent-neural-network-based technique dynamically alters pseudorandom-generator constraints using coverage feedback from simulation of the design under verification; reported experiments show that coverage closure is achieved much sooner and a small set of high-coverage stimuli can be isolated for regression tests. Automation of Processor Verification Using Recurrent Neural Networks
[7] Coverage-directed test selection generates many random tests, uses supervised learning from coverage feedback to select the subset most likely to increase functional coverage, and prioritizes that subset for simulation when stimulus generation is significantly cheaper than simulation. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[8] Coverage-directed test selection can reduce manual constraint writing, prioritize effective tests, reduce verification resource consumption, and accelerate coverage closure on a large real-life industrial hardware design. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[9] Novelty-driven verification learns to identify and simulate stimuli that differ from previously simulated stimuli, reducing the number of simulations and increasing testing efficiency; it has complementary strengths and limitations relative to coverage-directed test selection. Hybrid Intelligent Testing in Simulation-Based Verification
[10] A hybrid intelligent testing approach combines coverage-directed test selection with novelty-driven verification to address each method's individual limitations, producing hardware testing that is both efficient and effective. Hybrid Intelligent Testing in Simulation-Based Verification
[11] RISC-V DV uses SystemVerilog with UVM to continuously generate RISC-V instruction streams from constrained-random descriptions, with each generated stream being a test case, and provides a high-level co-simulation interface for comparing results between simulators through execution log files. Efficient Cross-Level Testing for RISC-V
[12] RISC-V DV has two disadvantages: generated instruction streams are restricted to avoid infinite loops and platform-dependent memory-access problems, and the framework has significant performance overhead because it is a generic simulator-support framework. Efficient Cross-Level Testing for RISC-V
[13] Constrained-random generators can produce hundreds of thousands of targeted instructions, but experience from traditional CPU vendors and observations in RISC-V cores indicate that simulation-based verification alone is inadequate, motivating additional techniques such as formal verification. RISC-V Microarchitecture Verification Approaches
[14] Formal methods can provide correctness guarantees, but are significantly more difficult to apply than simulation-based methods and, due to complexity and potential scalability issues, should be complemented by simulation-based methods. Efficient Cross-Level Testing for RISC-V
[15] A hybrid verification strategy is needed: formal verification is valuable for exhaustively exploring input combinations against ISA-specified behavior, while simulation is necessary to validate all modules of a large processor, ensure correct SoC integration, and run software on the device under test. RISC-V Microarchitecture Verification Approaches
[16] Verification is never truly complete; the practical view is that verification is sufficient when residual risk is manageable, and simulation-based verification can produce extensive coverage reports that indicate a large portion of the design has been exercised and specific bug classes have been found, but cannot guarantee the absence of defects. RISC-V Microarchitecture Verification Approaches
[17] Processor coverage is not just instruction-level or decoder coupling; it also depends on instruction sequences and dynamic events inside the pipeline, and when exhaustive verification is impossible, heuristic methods such as running real software workloads for extended periods from the user's perspective are recommended. RISC-V Microarchitecture Verification Approaches