Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
Paper“Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study” presents an efficient RISC-V processor-verification approach based on unrestricted, generic on-the-fly instruction-stream generation and tight co-simulation between an Instruction Set Simulator and an RTL core. In the reported TGF-series RISC-V core case study, the approach found several serious bugs, with each described bug found in less than five minutes, and generated/co-simulated 226 million instructions in one hour.
First seen 5/25/2026
Last seen 6/8/2026
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WIKI
Overview
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study is a paper on simulation-based processor verification for RISC-V RTL cores. The evidence describes an approach that avoids restrictions on generated instructions and uses a lightweight test-generation process together with tight co-simulation between an Instruction Set Simulator (ISS) and an RTL core.
Approach
NEIGHBORHOOD
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50 connectionsThe paper presents a case study on verifying the MINRES TGF RTL core.
The paper proposes a cross-level testing approach for processor verification.
The paper compares its approach with RISC-V DV in terms of efficiency.
The paper introduces an instruction generation algorithm for on-the-fly test generation.
The paper mentions constraint-based test generation as a related approach.
The paper mentions formal verification approaches as complementary to simulation-based methods.
The paper mentions riscv-formal as a notable formal verification approach for RISC-V.
The paper targets the RV32I ISA configuration in its case study.
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification mentions → 95% 2e
The paper cites Genesys-pro as related work on test program generation.
This related paper introduces the cross-level co-simulation approach that the current paper builds upon.
The paper cites the RISC-V VP paper as the source of its ISS reference model.
The paper compares its approach with the cross-level co-simulation approach from this related work.
The paper introduces on-the-fly instruction stream generation as part of its approach.
The paper's approach is centered around instruction stream generation for processor verification.
The paper introduces the instruction fetch matching algorithm to solve the synchronization challenge between RTL core and ISS.
The paper uses Verilator to obtain a C++ description of the RTL core.
The paper generates instructions on-the-fly during simulation.
The paper uses co-simulation between ISS and RTL core for verification.
The paper uses an ISS as a reference model for RTL verification.
The paper targets the RISC-V ISA for processor verification.
The paper focuses on RTL verification of RISC-V processors.
The co-simulation testbench is implemented in SystemC.
The paper uses TLM for memory abstraction in its co-simulation testbench.
The paper uses SpinalHDL to obtain the Verilog RTL implementation of the TGF core.
The paper uses the RISC-V VP's ISS as the reference model.
The paper introduces a co-simulation testbench for processor verification.
The paper uses opcode injection as a modification to the instruction generation.
The paper uses instruction field mutation to guide test generation towards interesting cases.
The paper uses instruction sequence generation as a third modification to guide test generation.
The paper discusses RISC-V Torture Test as a related model-based approach and contrasts its limitations.
The paper presents the co-simulation testbench as a central artifact of its approach.
The paper mentions model-based test generation as a related approach.
Vladimir Herdt is listed as an author of the paper.
Daniel Große is listed as an author of the paper.
Rolf Drechsler is listed as an author of the paper.
The paper tests and discusses CSR behavior extensively.
The paper tests trap handling as part of its comprehensive verification.
The paper is affiliated with DFKI GmbH.
The paper mentions coverage-guided fuzzing tailored for ISS-level verification as a related research direction.
The paper mentions Bayesian network-based test generation as a related approach.
The paper mentions machine learning techniques as an alternative approach to test generation.
The paper cites this work as a constraint-solving based test generation approach.
The paper cites this work as an optimized test generation framework using abstract CSP.
The paper cites MicroTESK as a specification-based tool for constructing test program generators.
The paper discusses coverage-guided fuzzing as a related approach and notes its limitations.
The paper uses simulation-based verification as its primary methodology.
The paper mentions bayesian network coverage-guided test generation as a related approach.
The paper mentions constrained-random test generation as used by RISC-V DV.
The paper addresses challenges related to the RTL core's pipeline during instruction matching.
The paper cites MicroTESK as related work on model-based test generation.
LINKED ENTITIES
43 linksVladimir Herdt AUTHORED_BY Extracted graph relationship
Daniel Große AUTHORED_BY Extracted graph relationship
Eyck Jentzsch AUTHORED_BY Extracted graph relationship
Rolf Drechsler AUTHORED_BY Extracted graph relationship
Cross-Level Testing INTRODUCES Extracted graph relationship
on-the-fly instruction stream generation USES Extracted graph relationship
Co-Simulation USES Extracted graph relationship
Instruction Set Simulator (ISS) USES Extracted graph relationship
MINRES The Good Folk (TGF) Series RTL core EVALUATES Extracted graph relationship
RISC-V ISA USES Extracted graph relationship
RTL verification USES Extracted graph relationship
SystemC USES Extracted graph relationship
TLM (Transaction Level Modeling) USES Extracted graph relationship
Verilator USES Extracted graph relationship
SpinalHDL USES Extracted graph relationship
RISC-V VP USES Extracted graph relationship
co-simulation testbench INTRODUCES Extracted graph relationship
instruction generation algorithm INTRODUCES Extracted graph relationship
opcode injection USES Extracted graph relationship
instruction field mutation USES Extracted graph relationship
instruction sequence generation USES Extracted graph relationship
riscv-dv COMPARES_WITH Extracted graph relationship
RISC-V Torture Test COMPARES_WITH Extracted graph relationship
Coverage-Guided Fuzzing COMPARES_WITH Extracted graph relationship
Formal Verification MENTIONS Extracted graph relationship
riscv-formal MENTIONS Extracted graph relationship
Simulation-Based Verification USES Extracted graph relationship
Model-Based Test Generation MENTIONS Extracted graph relationship
constraint-based test generation MENTIONS Extracted graph relationship
bayesian network coverage-guided test generation MENTIONS Extracted graph relationship
constrained-random test generation MENTIONS Extracted graph relationship
pipeline USES Extracted graph relationship
Control and Status Register (CSR) USES Extracted graph relationship
trap handling USES Extracted graph relationship
RV32I USES Extracted graph relationship
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification MENTIONS Extracted graph relationship
MicroTESK: specification-based tool for constructing test program generators MENTIONS Extracted graph relationship
Extensible and configurable RISC-V based virtual prototype MENTIONS Extracted graph relationship
Towards specification and testing of RISC-V ISA compliance MENTIONS Extracted graph relationship
Verifying Instruction Set Simulators using Coverage-guided Fuzzing MENTIONS Extracted graph relationship
Closing the RISC-V compliance gap: Looking from the negative testing side MENTIONS Extracted graph relationship
Instruction Stream Generation USES Extracted graph relationship
DFKI GmbH AUTHORED_BY Extracted graph relationship
CITATIONS
7 sources7 citations — click to expand
[1] The paper uses unrestricted or generic on-the-fly instruction-stream generation and ISS/RTL co-simulation. Efficient Cross-Level Testing for
[2] The case study concerned a pipelined industrial RISC-V TGF-series core and found several serious bugs. Efficient Cross-Level Testing for
[4] The visible bug list includes CSR access, MEPC, MISA, MTVAL/ECALL, MTVEC MODE, EBREAK/MCAUSE, FENCE/FENCE.I, MINSTRET/MCYCLE trap behavior, and MINSTRET update issues. Efficient Cross-Level Testing for
[5] In one hour, the approach generated and co-simulated 226 million instructions: 12 million illegal and 214 million legal, with 156 million legal instructions completing normally and 58 million causing an exception or trap. Efficient Cross-Level Testing for
[6] The reported average throughput was 63 thousand instructions per second and 229 thousand RTL-core cycles per second. Efficient Cross-Level Testing for
[7] The paper’s future work includes parallelized test sessions, FPGA acceleration, interrupt-interface testing, additional RISC-V ISA extensions, and RTL-aware coverage and feedback mechanisms. Efficient Cross-Level Testing for