TLM (Transaction Level Modeling)

Concept

TLM (Transaction Level Modeling) is presented in the evidence as a SystemC-associated modeling approach that abstracts communication into transactions, commonly for high-level algorithmic models. A TLM transaction object carries a command such as read or write, a data payload, and an address, and can be used to provide a unified memory abstraction across RTL and ISS components in co-simulation.

First seen 5/26/2026

Last seen 5/30/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

TLM (Transaction Level Modeling) is described as part of the relevant background for SystemC-based co-simulation. The evidence states that SystemC in combination with TLM is an industry-proven modeling standard for building designs at different levels of abstraction. In that setting, communication can be implemented either with signals, which are commonly used for RTL models, or abstracted using TLM transactions, which are commonly used for high-level algorithmic models.

Transaction structure

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RELATIONSHIPS

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Co-Simulation Testbench ← uses 100% 2e

The co-simulation testbench uses TLM for memory abstraction.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses TLM for memory abstraction in its co-simulation testbench.

co-simulation testbench ← uses 100% 2e

The co-simulation testbench uses TLM transactions for memory abstraction.

LINKED ENTITIES

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SystemC used_with The evidence states that SystemC in combination with TLM is an industry-proven modeling standard and that the co-simulation testbench is implemented in SystemC and uses TLM.

CITATIONS

6 sources

6 citations — click to expand

[1] SystemC with TLM is an industry-proven modeling standard for designs at different levels of abstraction.

[2] Communication can be implemented using signals for RTL models or abstracted using TLM transactions for high-level algorithmic models.

[3] A TLM transaction object consists essentially of a command such as read or write, the data payload, and the address.

[4] In the example memory interface, a TLM generic payload transaction named gp supplies address, access length, and data pointer, and the command determines whether read or write operations are performed.

[5] In the described co-simulation testbench, memory interfaces translate between RTL core signals and TLM transactions, enabling a unified memory abstraction for the RTL core and ISS.

[6] The referenced co-simulation testbench is implemented in SystemC and uses TLM.