co-simulation testbench
CodeArtifactA co-simulation testbench for cross-level RISC-V processor verification that drives an RTL core and an ISS with an unrestricted instruction stream, uses a core adapter to observe completed RTL instructions, and applies instruction-stream matching plus randomized instruction generation to expose mismatches.
First seen 5/29/2026
Last seen 5/30/2026
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Overview
The co-simulation testbench is the verification setup described for cross-level testing of a pipelined 32-bit RISC-V core. Its purpose is to run an RTL core and an instruction set simulator (ISS) against an effectively endless, unrestricted instruction stream while detecting mismatches between the two models.
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7 connectionsThe paper introduces a co-simulation testbench for processor verification.
The co-simulation testbench implements the co-simulation technique.
The co-simulation testbench is implemented using SystemC.
The co-simulation testbench uses TLM transactions for memory abstraction.
The co-simulation testbench includes a core adapter to interface with the RTL core.
The co-simulation testbench includes a test controller to orchestrate the co-simulation.
The instruction generation algorithm is part of the co-simulation testbench.
LINKED ENTITIES
7 linksEfficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study INTRODUCES Extracted graph relationship
Co-Simulation IMPLEMENTS Extracted graph relationship
SystemC USES Extracted graph relationship
TLM (Transaction Level Modeling) USES Extracted graph relationship
core adapter USES Extracted graph relationship
test controller USES Extracted graph relationship
instruction generation algorithm PART_OF Extracted graph relationship
CITATIONS
8 sources8 citations — click to expand
[1] The co-simulation testbench is part of a cross-level RISC-V processor verification setup that runs an RTL core and ISS with an unrestricted instruction stream. Efficient Cross-Level Testing for
[2] The core adapter hides core implementation details, observes internal pipeline-related signal changes, notifies the test controller on completed instructions, preserves order for illegal instructions, and provides RTL register access for comparison with the ISS. Efficient Cross-Level Testing for
[3] Instruction stream matching is needed because RTL prefetching, jumps, and traps can make the RTL core and ISS fetch different instruction sequences or fetch them at different times. Efficient Cross-Level Testing for
[4] The matching mechanism compares ISS fetch requests with a queue of pending instructions delivered to the RTL core and reports a mismatch if the ISS fetches an instruction not delivered to the RTL core. Efficient Cross-Level Testing for
[5] The setup avoids feeding completed RTL instructions directly to the ISS because doing so would rely on correct instruction propagation inside the RTL core under test. Efficient Cross-Level Testing for
[6] The instruction generator baseline fully randomizes generated instructions, and guidance mechanisms include opcode injection, field mutation, and instruction-sequence generation. Efficient Cross-Level Testing for
[7] Field mutation rules include special immediate values, register-field relationships such as RD equals RS1 or RS2, RD set to zero, RS1 matching RS2, and mutation of CSR selectors to supported CSRs. Efficient Cross-Level Testing for
[8] The algorithm shown in the paper starts a sequence with 1% probability, injects a random valid opcode with 98% probability, and applies a field mutation with 20% probability. Efficient Cross-Level Testing for