Co-Simulation Testbench

Concept

A co-simulation testbench for cross-level processor verification coordinates an RTL core and an instruction-set simulator (ISS) under a shared, on-the-fly instruction stream. In the cited design, the testbench is implemented in SystemC, uses Transaction Level Modeling (TLM) for memory abstraction, includes a core adapter and test controller interaction, and relies on instruction-stream matching to keep RTL and ISS execution comparable despite pipeline prefetching, jumps, and traps.

First seen 5/25/2026

Last seen 5/26/2026

Evidence 6 chunks

Wiki v1

WIKI

Co-Simulation Testbench

A Co-Simulation Testbench is a verification setup that runs an RTL processor core together with an instruction-set simulator (ISS) and compares their behavior while feeding both from a generated instruction stream. In the cited cross-level processor-verification approach, the co-simulation testbench is used to feed an on-the-fly, endless instruction stream to both the ISS and the RTL core. [C1]

Implementation basis

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RELATIONSHIPS

6 connections

SystemC uses → 100% 2e

The co-simulation testbench is implemented in SystemC.

TLM (Transaction Level Modeling) uses → 100% 2e

The co-simulation testbench uses TLM for memory abstraction.

Instruction Fetch Matching ← part of 90% 2e

The co-simulation testbench includes instruction fetch matching as a component.

Co-Simulation ← uses 90% 2e

Co-simulation is realized via the co-simulation testbench that connects ISS and RTL core.

Instruction Set Simulator (ISS) uses → 100% 2e

The co-simulation testbench uses the ISS as a reference model for comparison with the RTL core.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← introduces 95% 2e

The paper presents the co-simulation testbench as a central artifact of its approach.

LINKED ENTITIES

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Instruction Stream Generator CONTAINS Extracted graph relationship

SystemC IMPLEMENTED_IN Extracted graph relationship

Transaction Level Modeling USES Extracted graph relationship

Core Adapter CONTAINS Extracted graph relationship

Test Controller CONTAINS Extracted graph relationship

CITATIONS

13 sources

13 citations — click to expand

[1] The co-simulation testbench feeds an on-the-fly endless instruction stream to both an ISS and an RTL core for cross-level processor verification.

[2] The co-simulation testbench is implemented in SystemC and uses TLM.

[3] TLM communication uses transaction objects that include a command, payload data, and an address.

[4] The RTL core has separate instruction and data memory interfaces, and the memory interfaces translate between RTL signals and TLM transactions; the ISS also uses two separate memory interfaces.

[5] The data memory is lazy and uses matching random seeds on RTL and ISS sides so both behave identically under the same data-memory access sequence.

[6] RTL instruction fetches generate new instructions on the fly, while ISS instruction fetches receive the corresponding RTL-fetched instruction through instruction-stream matching.

[7] Instruction-stream matching is necessary because RTL prefetching, jumps, and traps can cause fetched and executed instruction sequences to diverge between RTL and ISS.

[8] The instruction-stream matcher uses a pending-instruction queue and reports a mismatch if the ISS fetch does not match an instruction delivered to the RTL core.

[9] The core adapter hides RTL implementation details, observes pipeline-related signal changes, and notifies the test controller when the RTL core completes an instruction while preserving order for illegal instructions.

[10] The core adapter provides access to RTL register values for comparison with the ISS.

[11] The completed instruction sequence from the core adapter is not directly fed to the ISS because doing so would rely on correct instruction propagation in the RTL core under test.

[12] The instruction stream generator enables endless unrestricted instruction generation, with a baseline algorithm that fully randomizes generated instructions.

[13] One generator modification injects a random opcode to create a valid instruction while keeping instruction fields randomized, helping cover legal instructions.