Test Controller
CodeArtifactThe Test Controller is the orchestration component in a SystemC co-simulation testbench for processor verification. It coordinates stepwise execution of an RTL core and an ISS reference model, compares their architectural state, and reports mismatches.
First seen 5/25/2026
Last seen 5/25/2026
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Overview
The Test Controller is the central orchestration component of a SystemC-based co-simulation testbench for processor verification. In the described setup, the testbench co-simulates an RTL core under test with an ISS reference model, and the Test Controller sits at the bottom center of the architecture as the component that drives and evaluates the co-simulation loop. [C1]
Role in the co-simulation loop
NEIGHBORHOOD
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[1] The Test Controller is part of a SystemC-based co-simulation testbench that co-simulates an RTL core under test with an ISS reference model.
[2] The Test Controller orchestrates the co-simulation by letting the RTL core execute one instruction, letting the ISS execute the same instruction, comparing execution states, and reporting an error on mismatch.
[3] A core adapter observes internal RTL core signal changes, notifies the Test Controller when an instruction completes, preserves correct order for illegal instructions, and provides RTL register values for comparison with the ISS.