Instruction Fetch Matching
ConceptInstruction Fetch Matching is a co-simulation technique for keeping an RTL processor core and an instruction set simulator aligned when the RTL core pre-fetches instructions that may later be discarded by jumps or traps. The method records RTL-fetched instructions in a pending queue with their program counters, then matches ISS fetch requests against both the ISS PC and the last completed RTL instruction, reporting a mismatch when no corresponding pending instruction exists.
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Overview
Instruction Fetch Matching—described in the evidence as instruction stream or instruction fetch matching—is used to feed the same on-the-fly generated instruction stream to a pipelined RTL core and an instruction set simulator (ISS). This is necessary because the RTL core can pre-fetch instructions ahead of execution, while the ISS fetches according to the instructions it has actually executed. As a result, jumps, traps, and short backward jumps can cause the RTL core and ISS to observe different apparent fetch sequences unless special matching is performed. [Purpose and problem]
Why simple PC matching is insufficient
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