Skip to content
STIMSMITH

Instruction Fetch Matching

Concept WIKI v1 · 5/25/2026

Instruction Fetch Matching is a co-simulation technique for keeping an RTL processor core and an instruction set simulator aligned when the RTL core pre-fetches instructions that may later be discarded by jumps or traps. The method records RTL-fetched instructions in a pending queue with their program counters, then matches ISS fetch requests against both the ISS PC and the last completed RTL instruction, reporting a mismatch when no corresponding pending instruction exists.

Overview

Instruction Fetch Matching—described in the evidence as instruction stream or instruction fetch matching—is used to feed the same on-the-fly generated instruction stream to a pipelined RTL core and an instruction set simulator (ISS). This is necessary because the RTL core can pre-fetch instructions ahead of execution, while the ISS fetches according to the instructions it has actually executed. As a result, jumps, traps, and short backward jumps can cause the RTL core and ISS to observe different apparent fetch sequences unless special matching is performed. [Purpose and problem]

Why simple PC matching is insufficient

A direct match based only on the program counter does not work in the described setup. The RTL core may pre-fetch instructions due to its pipeline, but those prefetched instructions may never execute if a jump or trap changes control flow. The evidence gives the example of a one-instruction backward jump from address 8 to address 4: the RTL core can begin pre-fetching again before the jump is fully completed, causing a new instruction to be generated for an address before the ISS has had the opportunity to fetch and execute the jump. [Prefetch and control-flow divergence]

Matching algorithm

The instruction stream maintains a queue of pending instructions in fetch order. Each pending entry stores both the generated instruction and the PC at which the RTL core fetched it. These are instructions already fetched by the RTL core but not yet consumed by the ISS. [Pending queue]

When the ISS requests its next instruction, the matching procedure receives the ISS PC together with the expected instruction, derived from the last completed instruction observed in the RTL core through the core adapter. It then searches the pending queue:

  1. Pop pending entries in fetch order.
  2. Compare the stored PC with the ISS PC.
  3. Compare the stored instruction with the expected instruction.
  4. If both match, return the instruction to the ISS.
  5. If the queue is exhausted without a match, report a mismatch between RTL core and ISS. [Algorithm behavior]

This avoids directly feeding the completed instruction sequence from the RTL core into the ISS. The evidence explicitly notes that doing so would compromise the test approach, because it would rely on correct instruction propagation inside the RTL core, which is the design under test. [Avoiding circular validation]

Role in the verification setup

Instruction Fetch Matching is part of a co-simulation setup that generates an endless, unrestricted instruction stream. The broader setup supports memory-access instructions, jump instructions including self-loops from on-the-fly generation, and special RISC-V CSR access instructions. Regardless of which instructions are generated, the RTL core and ISS are expected to behave identically on observable architectural state, such as register updates. [Co-simulation role]

The core adapter supports this process by observing internal RTL pipeline signal changes, notifying the test controller whenever the RTL core completes an instruction, preserving correct order in the presence of illegal instructions, and exposing RTL register values for comparison with the ISS. [Core adapter and test controller]

LINKED ENTITIES

3 links
Co-Simulation USED_IN
Test Controller USES
Co-simulation USED_IN

CITATIONS

7 sources
7 citations
[1] Purpose and problem
[2] Prefetch and control-flow divergence
[3] Pending queue
[4] Algorithm behavior
[5] Avoiding circular validation
[6] Co-simulation role
[7] Core adapter and test controller