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Test Controller

CodeArtifact WIKI v1 · 5/25/2026

The Test Controller is the orchestration component in a SystemC co-simulation testbench for processor verification. It coordinates stepwise execution of an RTL core and an ISS reference model, compares their architectural state, and reports mismatches.

Overview

The Test Controller is the central orchestration component of a SystemC-based co-simulation testbench for processor verification. In the described setup, the testbench co-simulates an RTL core under test with an ISS reference model, and the Test Controller sits at the bottom center of the architecture as the component that drives and evaluates the co-simulation loop. [C1]

Role in the co-simulation loop

The Test Controller repeats a three-step verification cycle: [C2]

  1. Let the RTL core execute one instruction.
  2. Let the ISS execute the same instruction.
  3. Compare the execution states of the RTL core and ISS, especially register state.

If the compared execution states differ, the controller reports an error; if no mismatch is found, the co-simulation continues until the available testing time is exhausted. [C2]

Interaction with the core adapter

The RTL core does not necessarily expose a single direct signal indicating that an instruction has completed. To hide these implementation details, a core adapter observes internal core signal changes, especially pipeline behavior, and notifies the Test Controller whenever the RTL core completes an instruction. The adapter also preserves correct instruction order for illegal instructions and provides access to RTL register values so they can be compared against the ISS state. [C3]

Relationship to instruction matching

Feeding the same instruction stream to the RTL core and ISS requires special handling because the RTL core may pre-fetch instructions that are later not executed after a jump or trap. Short jumps can also cause RTL instruction fetches before the ISS has reached the same fetch point. [C4]

The described instruction matching approach keeps a queue of pending instructions fetched by the RTL core but not yet consumed by the ISS. Matching uses both the ISS program counter and the expected instruction derived from the last completed RTL instruction; a match returns the instruction to the ISS, while failure reports a mismatch between RTL core and ISS. [C5]

Error handling

The Test Controller reports errors when the architectural execution states of the RTL core and ISS diverge. Separately, the instruction matching mechanism reports a mismatch if the ISS attempts to fetch an instruction that was not delivered to the RTL core. [C2] [C5]

LINKED ENTITIES

2 links
Co-Simulation Testbench CONTAINS
Instruction Fetch Matching USES

CITATIONS

5 sources
5 citations
[1] The Test Controller is part of a SystemC-based co-simulation testbench that co-simulates an RTL core under test with an ISS reference model.
[2] The Test Controller orchestrates the co-simulation by letting the RTL core execute one instruction, letting the ISS execute the same instruction, comparing execution states, and reporting an error on mismatch.
[3] A core adapter observes internal RTL core signal changes, notifies the Test Controller when an instruction completes, preserves correct order for illegal instructions, and provides RTL register values for comparison with the ISS.
[4] Instruction stream matching is needed because RTL pre-fetching and jumps or traps can cause the RTL core and ISS to observe different fetch sequences if handled naively.
[5] The instruction matching algorithm queues RTL-fetched pending instructions with their PCs, matches them against the ISS PC and expected instruction, returns the instruction on a match, and reports a mismatch otherwise.