Core Adapter

CodeArtifact

The Core Adapter is a code artifact in a SystemC-based co-simulation testbench for processor verification. It abstracts RTL-core implementation details by observing internal core signal changes, especially pipeline activity, notifying the test controller when an instruction completes, preserving ordering for illegal instructions, and exposing RTL register values for comparison with an ISS reference model.

First seen 5/25/2026

Last seen 6/5/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

The Core Adapter is part of a SystemC-based co-simulation setup for processor verification. The broader testbench co-simulates an RTL core under test with an ISS reference model, while a test controller repeatedly executes one instruction on the RTL core, executes the same instruction on the ISS, and compares their execution states, especially register state. [C1]

Within that setup, the Core Adapter provides a clean testing interface over implementation-specific RTL details. It is introduced because detecting instruction completion in a pipelined RTL core can require detailed knowledge of pipeline behavior, including multi-cycle operations, delays, and gaps. [C2]

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

4 connections

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← introduces 95% 1e

The paper introduces the Core-Adapter for handling micro-architectural details.

pipelining uses → 90% 1e

The Core-Adapter handles pipelining-related fetch behavior differences between ISS and RTL core.

Cross-Level Processor Verification part of → 90% 1e

The Core-Adapter is a component of the cross-level processor verification framework.

Co-simulation part of → 90% 1e

The Core-Adapter is used in the co-simulation to handle micro-architectural differences.

LINKED ENTITIES

2 links

Co-Simulation Testbench CONTAINS Extracted graph relationship

MINRES TGF RISC-V Core MONITORS Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] The co-simulation testbench is implemented in SystemC and coordinates execution between an RTL core under test and an ISS reference model, with the test controller executing and comparing one instruction at a time.

[2] The Core Adapter hides RTL-core implementation details, observes internal core signal changes especially in the pipeline, notifies the test controller when the RTL core completes an instruction, preserves correct order for illegal instructions, and provides access to RTL register values.

[3] Instruction-stream matching is complicated by RTL prefetching, jumps, and traps; the completed instruction sequence is not directly fed from the Core Adapter to the ISS because that would rely on instruction propagation in the RTL core under test.